Work

CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems

Year: 2026

Type: preprint

Abstract: This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implements the rv64gch ISA and features advanced support for real-time execution, including TLB partitioning and locking for predictable address translation, a dynamically reconfigurable scratchpad mode in the L1 caches for deterministic memory access, and low-latency interrupt handling via an enhanced interrupt controller combined with hardware-assisted context stacking. With real-time features enabled, CVA6-RT achieves an interrupt latency of 12 cycles, comparable to that of simpler Arm Cortex-M microcontrollers, and 10x lower than the baseline CVA6 core.

Source: arXiv (Cornell University)

DOI: 10.48550/arxiv.2606.26177

Authors: Zelioli, Enrico, Reinwardt, Christopher, Wistoff, Nils, Balas, Robert, Ottaviano, Alessandro, Benini, Luca, Garofalo, Angelo

Institutions: ETH Zurich, Integrated Systems Laboratory, GNA University, University of Bologna

Topic: Real-Time Systems Scheduling

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W7166169853

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