Work

POSTER: Hardware Acceleration for Graph Neural Networks

Year: 2026

Type: conference-paper

Abstract: Graph Neural Networks deliver state-of-the-art performance across graph-structured domains but remain difficult to accelerate on modern GPUs. Their sparse neighborhood aggregation produces non-coalesced, bandwidth-intensive memory access that causes pipeline stalls and leaves GPU arithmetic units underutilized. We propose Near-Cache Compute (NCC), a microarchitectural extension placing lightweight FP32 FMA units adjacent to each GPU L2 cache bank, enabling FP32 operations to execute at L2 latency rather than incurring a DRAM round-trip. A three-phase SASS compiler pass maps eligible LDG → ALU → STG patterns to NCC ISA extensions without application-level changes. Evaluated on Accel-Sim against an A100 baseline, NCC achieves 1.44 × speedup on LightGCN, 1.08 × on ExpressGNN, and 1.06 × on GIN, with kernel-level gains of up to 9.5 × on the most memory-bound aggregation kernels.

Source: ACM International Conference on Computing Frontiers (CF)

DOI: 10.1145/3801487.3805612

Authors: Cory Davis, Patrick Stockton, Eugene B. John, Jeeho Ryoo, Ebod Shojaei

Institutions: The University of Texas at San Antonio, Fairleigh Dickinson University, University of British Columbia

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Funders: National Science Foundation, Semiconductor Research Corporation

Award: SHF: Medium: Collaborative Research: Predictive Modeling for Next-generation Heterogeneous System Design