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Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Year: 2026

Type: article

Abstract: Explore the article titled Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology from IJIRT Volume 13, Issue 2. This study evaluates the effectiveness of teaching programs on waste management knowledge among women.

Source: International Journal of Innovative Research in Technology

Authors: Suroju Sai Santhosh Kumar, Udutha Saritha

Institution: Vaagdevi College of Engineering

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

OpenAlex ID: W7170918439

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