Work

Enhancement in Charge-Trapping Efficiency for InGaZnO Vertical-Channel Memory Transistors via Gate-Stack Engineering: Validation in the 40 nm Scaling Regime

Year: 2026

Type: article

Source: ACS Applied Materials & Interfaces

DOI: 10.1021/acsami.6c09875

Authors: Yu-Jin Jung, Chi-Sun Hwang, Sung-Min Yoon

Institutions: Kyung Hee University, Electronics and Telecommunications Research Institute

Language: English

Topic: Thin-Film Transistor Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Research Foundation of Korea

Award: G4722613753

OpenAlex ID: W7203834538

FWCI:

Cites: 64

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