Work

A Delay‐Locked Loop Operating Between 2.5 MHz and 1 GHz With a False‐Lock Mitigation Strategy

Year: 2026

Type: article

Abstract: ABSTRACT A new delay‐locked loop (DLL) design and a current‐starved delay‐cell structure are proposed to mitigate false locking in a 180‐nm CMOS process. The designed DLL is intended for use in ultrasound imaging applications. The external reference voltage () and the control voltage () obtained at the charge pump output are connected to the inputs of a comparator. This comparator output is used to adjust the delay range of the delay cell, thereby helping the DLL avoid false‐lock issues. As a second major contribution, a wide operating frequency range is achieved by modifying the delay range. Post‐layout simulations were performed across process, voltage, and temperature (PVT) corners of the voltage‐controlled delay cell (VCDL), thereby obtaining for each corner in the DLL. Then, simulations were performed across all process corners at temperatures of 0 °C, 27 °C, and 100 °C, as well as at supply voltages of 1.6, 1.8, and 2 V. It was observed that the DLL avoided false lock conditions and properly locked in each PVT corner combination. The layout of the entire DLL block occupies 0.084 mm 2 . Power dissipation was measured at 0.59, 3.4, and 5.03 mW at 2.5, 357 MHz, and 1 GHz, respectively.

Source: International Journal of Circuit Theory and Applications

DOI: 10.1002/cta.70621

Authors: Emre Altuner, Mustafa Berke Yelten

Institution: Istanbul Technical University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: bronze

Funder: Istanbul Teknik Üniversitesi

Award: G6828055773