Work

Co-Design and Logic Synthesis Optimization of a Low-Power Custom RISC-V Vector Accelerator for Edge-AI Applications

Year: 2026

Type: other

Abstract: A Computer Architecture research paper that accelerates deep learning inference on edge microcontrollers using a custom RISC-V vector hardware coprocessor, optimized at the gate level via AI-driven logic synthesis to maximize throughput and energy efficiency.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.23019663

Author: Cademia, Mary Grace

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: green

OpenAlex ID: W7214584620

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Related to: 10