Year: 2026
Type: article
Abstract: In recent years, edge computing has been developing very fast, and it is being used in smart homes, wearable devices, and self-driving cars, so these applications are putting higher and higher demands on embedded microprocessors, especially in terms of power saving, quick response, and customizing for specific uses. This paper mainly gives a general review of embedded microprocessor technologies that are based on the open RISC-V instruction set architecture. First of all, it introduces the basic structure of embedded microprocessors and the main modular design ideas of the RISC-V instruction set architecture (ISA); then, it summarizes recent research progress in three important technical areas, which are processor core design, interrupt handling methods, and lightweight branch prediction techniques. The main findings show that hardware-optimized interrupt schemes have cut down latency to a level similar to proprietary ARM cores, and at the same time, area-efficient branch predictors can also effectively reduce pipeline stalls in situations where resources are limited. However, there are still two big problems, namely ecosystem immaturity and architectural fragmentation, and these remain important obstacles that prevent wider use. In the end, the paper talks about possible solutions, including the ratification of standardized extensions and the development of unified software toolchains, and it is expected that these efforts will help RISC-V become a more stable foundation for next-generation embedded computing systems.
Author: Jinghui Yi
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7214609040