Work

Variability-Aware Memristor Circuit for Hierarchical Bayesian Temporal Sampling

Year: 2026

Type: preprint

Abstract: Bayesian neural networks (BNNs) require hardware capable of storing and sampling probabilistic synaptic weights. While population coding exploits device-to-device (D2D) variability to encode weight distributions, temporal sampling instead requires controlled and reproducible stochastic fluctuations, making its hardware implementation particularly challenging. Here, we demonstrate a memristor-based temporal-coding circuit that combines three analog memristor devices per synaptic weight to encode its mean and standard deviation with an externally injected white-noise source for sample generation. A dedicated fluctuation-amplification stage provides controllable temporal stochasticity, while a hierarchical training algorithm explicitly models device-to-device variability and temporal noise to ensure robust Bayesian inference under hardware non-idealities. On the MIT-BIH arrhythmia classification task, the proposed approach achieves a 2.7-fold reduction in memory footprint compared with an equivalent population-coding implementation, while preserving Bayesian inference accuracy and uncertainty estimates.

Source: Research Square

DOI: 10.21203/rs.3.rs-11061798/v1