ZVS-Inclusive Output Voltage Ripple Minimization for Modular Output-Paralleled Resonant CLLC Converters
Year: 2026
Type: article
Abstract: This work develops a deadtime-transition-inclusive multi-harmonic framework to identify and model the root causes of output voltage ripple distortion in practical modular Input Parallel Output Parallel (IPOP) resonant DC-DC converters. The proposed formulation captures key non-idealities, including resonant tank parameter mismatch, digital controller quantization, and output termination impedance asymmetry. A frequency-phase coordinated intermodule synchronous phase-shifted PWM strategy, termed PFM + PSM + Adaptive Phase Interleaving (API), is derived to analytically relate modulation control variables to output ripple while simultaneously enforcing zero-voltage switching (ZVS) across all devices. A holistic circuit physics-informed optimization framework is established to minimize peak output voltage ripple subject to ZVS and balanced current sharing constraints, with a harmonic diagnostic metric$\gamma _{1}$introduced to characterize the interleaving effectiveness achieved across load and gain operating conditions. The approach enables balanced current sharing, tight voltage regulation, and optimized ripple performance under load, voltage gain, and circuit parameter variations. The ripple performance of the proposed modulator is comparatively analyzed against existing IPOP CLLC modulation schemes using experimentally obtained ripple waveforms at$600\text{V}$-$28\text{V}$and$29\text{V}$, at power levels of$1600\text{W}$and$800\text{W}$.
Authors: Shubham Mungekar, Ayan Mallik
Language: English
Topic: Advanced DC-DC Converters
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,645
OpenAlex ID: W7216272727