Design space exploration of structural parameters for temperature effect inversion in saddle MOSFET
Year: 2026
Type: article
Abstract: This paper presents a novel device-level approach for controlling the temperature effect inversion (TEI) phenomenon in saddle metal–oxide–semiconductor field-effect transistors (MOSFETs). Previous studies on TEI have primarily focused on circuit-level compensation techniques, while systematic investigations from a device-structural perspective remain limited. In this work, the impact of key structural parameters of saddle MOSFETs on temperature-dependent propagation delay characteristics is analyzed. Technology computer-aided design simulation results demonstrate that structural modifications can effectively regulate delay inversion behavior in the subthreshold region. Device-level control of TEI directly influences both the propagation delay and the TEI operating range (TEI OR ) of circuits. By varying structural parameters, including recess depth, gate width, and side depth, both the TEI OR and the propagation-delay utilization range can be expanded. Among these parameters, gate width exhibits the highest effectiveness, increasing the TEI OR by up to 33%. These results indicate that TEI can be actively controlled through device structural engineering rather than relying solely on circuit-level techniques, providing valuable design guidelines for temperature-adaptive and thermally adaptive and TEI-aware digital complementary metal–oxide–semiconductor circuit applications.
Authors: Sunghyuk Lee, Woojoo Lee, Il Hwan Cho
Institutions: Myongji University, Chung-Ang University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
Awards: G2567167500, G2862973551, G2979250575
OpenAlex ID: W7220917520