Work

Temperature dependent analysis of the impact of interface traps on source-to-drain tunneling in UTB independent DG MOSFETs using a band-structure based simulation approach

Year: 2026
Type: article
Abstract: In Ultra-Thin Body (UTB) MOSFETs, Source-to-Drain Tunneling (SDT) is likely to manifest significantly and degrade device performance, due to which it is important that these effects are accurately quantified, particularly at lower device temperatures. Additionally, these SDT effects are likely to be further impacted by the presence of interface trap states. Therefore, with a view to consider these effects accurately in a UTB Independent Double Gate (IDG) MOSFET structure, where Quantum Confinement Effects are likely to manifest significantly, in this work we use the $sp^{3}d^{5}s^{*}$ based tight-binding method to accurately determine the band structure through which the channel electrostatics and drain currents are then estimated, from low device temperatures to room temperature, while initially considering a passivated front and back channel/oxide interfaces. This study helps us to clearly elucidate the impact of back gate oxide thickness, back gate voltage and channel thickness variations on the 2-D Channel Electrostatics as well as critical device performance parameters, such as the Sub-Threshold Swing (SS), over a wide range of device temperatures. Further, in order to provide a more realistic appraisal of the performance of these UTB IDG MOSFETs, we consider a variety of passivation conditions at the front and back SOI channel/oxide interface. Through this approach, we develop a clearer understanding of the impact of different device conditions on critical performance metrics of the transistor, over different device temperatures, thus also providing the possibility to control the impact of interface trap states on device performance through the back gate.
Language: English
Open Access status: bronze
OpenAlex ID: W7221568907
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