Work

Reliability prediction of ESD and electro-thermal degradation in SiC MOSFETS for energy storage

Year: 2026

Type: article

Abstract: Representative 1200 V planar SiC MOSFET and Si-IGBT cells are compared within a common device-level TCAD reliability-prediction framework, spanning sub-microsecond pulse electrothermal response and long-duration bias-temperature-induced interface degradation. Under a 10 A, 100 ns current pulse, the SiC cell exhibits a 4.70% lower peak terminal voltage (2392 V versus 2510 V) but an approximately 40% higher local peak lattice temperature (1313 K versus 938 K). After 180 h at 150 °C with V GS = 15 V and V DS = 0 V, the simulated on-state-current reductions are 21.65% for the SiC MOSFET and 4.64% for the Si-IGBT. Under off-state blocking stress at V GS = 0 V and V DS = 1200 V, the corresponding reductions are 0.12% and 10.87%, reversing the degradation ordering. Spatially resolved electric field, carrier energy, impact ionization, lattice temperature, and interface-trap distributions explain these stress- and metric-dependent responses. By covering both stress regimes, the framework addresses a gap in device-level TCAD reliability analysis for SiC power devices. Its modeling workflow can be transferred to other structures by updating device parameters and electrical and thermal boundary conditions, providing a reusable basis for reliability prediction, device design, and process optimization.

Source: Journal of Physics D Applied Physics

DOI: 10.1088/1361-6463/aeb4c5