PAHT: Process-Aware History Tracking for Fast Read Retry in High-Capacity 3D NAND SSDs
Year: 2026
Type: article
Abstract: While NAND flash memory has continuously increased its storage capacity, capacity-centric techniques have also exacerbated reliability problems. Conventionally, SSDs address reliability issues by incorporating read-retry operations that search for the optimal read reference voltage (VOPT). Read-retry reduces raw bit error rates (RBERs), but it significantly degrades read performance because multiple read iterations are required to complete a single host read request. To minimize this overhead, we propose Process-Aware History Tracking (PAHT), a novel technique that eliminates unnecessary read iterations during read-retry. PAHT is motivated by two observations: (i) VOPT does not need to be updated for a long interval, and (ii) the VOPT offset between wordlines (WLs) is identical across blocks in a chip. Our proposal integrates two optimizations. First, when a read on a given WL succeeds, we record and reuse the VOPT for future reads to the same WL. Second, we keep only one VOPT per block. For other WLs, we determine the VOPT using a predefined offset table that accounts for process variability in 3D flash memory. Based on comprehensive characterizations using 160 real 3D flash chips, system evaluations show that PAHT improves SSD performance by 58.3% on average by reducing read-retry invocations.
Source: Eng—Advances in Engineering
DOI: 10.3390/eng7100563
Institution: Kyungpook National University
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,448
OpenAlex ID: W7222098425