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Split-gate MOSFET with a source-connected P+ buffer for gate-oxide field suppression and current-path modulation

Year: 2026
Type: article
Abstract: The curvature-induced geometrical effect in split-gate metal–oxide–semiconductor field-effect transistors (SG-MOSFETs) can lead to electric-field crowding at the gate-oxide corner and an elevated short-circuit current level, thereby accelerating gate-oxide degradation and thermal failure. To address this issue, this paper proposes an SG-MOSFET with a source-connected heavily doped P-type buffer region, referred to as the source-connected P+ buffer split-gate MOSFET (SG-PS-MOSFET), to improve gate-oxide field distribution and short-circuit ruggedness. Based on two-dimensional electrothermal TCAD simulations, the proposed P-type buffer weakens the coupling between the high drain-side potential and the gate-oxide corner in the blocking state while enhancing depletion in the junction field-effect transistor region and compressing the effective electron current path under short-circuit stress. Compared with the SG-MOSFET, the SG-PS-MOSFET reduces the switching loss while introducing only a slight increase in on-resistance from 42 to 45.6 mΩ. The total switching energy is reduced from 617.86 to 397.14 μJ, corresponding to a reduction of 35.72%. Meanwhile, the peak electric field at the gate-oxide corner in the blocking state is reduced from 3.48 to 1.95 MV/cm, and the short-circuit withstand time is extended from 10.6 to 14.5 μs. These results demonstrate that the source-connected P+ buffer achieves a favorable balance among high-frequency switching performance, gate-oxide electric-field stress, and short-circuit ruggedness with only a small on-resistance penalty.
Source: AIP Advances
DOI: 10.1063/5.0355163
Language: English
Open Access status: gold
Estimated APC paid: $1,350
OpenAlex ID: W7222326580
FWCI:
Cites: 33
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Related to: 10