Year: 2026
Type: article
Abstract: ABSTRACT Area‐type memristors are attractive for analog in‐memory computing, but their use is often limited by parasitic charge storage, causing readout drift, non‐pinched hysteresis, and degraded readout fidelity. We show that near‐ideal area‐type switching emerges within a tunneling‐governed transport regime in ultrathin layers that suppresses charging‐related readout artifacts. By varying the thickness in TiN/Ta 2 O 5 /Pt in a range of 3–10 nm, we reveal the transition from filamentary switching to near‐short‐circuit transport with two gradual‐switching modes with different readout stability. The 5–6 nm thickness window suppresses non‐pinched hysteresis and short‐time drift while preserving analog switching, yielding nearly polarity‐symmetric hysteresis and readout, clear area scaling, and continuous near‐linear conductance modulation. Our analysis indicates that trap‐assisted tunneling dominates the stabilized‐state response, whereas ionic redistribution governs pristine‐state reconstruction and the stability boundaries. A compact model is derived for the 5 nm device which reproduces the quasi‐static I–V behavior and the dynamic resistance evolution based on pulse‐width‐dependent characteristics. The verified model is provided as Verilog‐A code enabling simulation in circuit design tools. Our results demonstrate that ultrathin scaling is a regime‐defining design rule for near‐ideal area‐type operation in oxide memristors, implying a fundamental approach to fabricating robust multi‐state memristors for in‐memory computing applications.
Source: Advanced Materials
DOI: 10.1002/adma.75393
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $6,070
OpenAlex ID: W7222334026