Split-Gate MOSFET With a Source-Connected P+ Buffer for Gate-Oxide Field Suppression and Current-Path Modulation
Year: 2026
Type: other
Abstract: The curvature-induced geometrical effect in split-gate metal-oxide-semiconductor field-effect transistors (SG-MOS) can lead to electric-field crowding at the gate-oxide corner and an elevated short-circuit current level, thereby accelerating gate-oxide degradation and thermal failure. To address this issue, this paper proposes a split-gate MOSFET with a source-connected heavily doped P-type buffer region, referred to as the source-connected P+ buffer split-gate MOSFET (SG-PS-MOS), to improve gate-oxide field distribution and short-circuit ruggedness. Based on two-dimensional electrothermal TCAD simulations, the proposed P-type buffer weakens the coupling between the high drain-side potential and the gate-oxide corner in the blocking state, while enhancing depletion in the junction field-effect transistor (JFET) region and compressing the effective electron current path under short-circuit stress. Compared with SG-MOS, SG-PS-MOS reduces the switching loss while introducing only a slight increase in on-resistance from 42 mΩ to 45.6 mΩ. The total switching energy is reduced from 617.86 μJ to 397.14 μJ, corresponding to a reduction of 35.72%. Meanwhile, the peak electric field at the gate-oxide corner in the blocking state is reduced from 3.48 MV/cm to 1.95 MV/cm, and the short-circuit withstand time (SCWT) is extended from 10.6 μs to 14.5 μs. These results demonstrate that the source-connected P+ buffer achieves a favorable balance among high-frequency switching performance, gate-oxide electric-field stress, and short-circuit ruggedness with only a small on-resistance penalty.
Source: AIP Publishing
Authors: Yi Liu, Jinchun Yan, Hengwen Yu, Haoyang Cui, Yingbo Yue
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7222364150