A Novel Technique of Bench-Marking Avalanche Ruggedness of SiC MOSFETs using the Third-Quadrant Safe-Operating-Area Energy
Year: 2026
Type: conference-paper
Abstract: This paper presents a novel technique of bench-marking avalanche ruggedness of SiC power MOSFETs by comparing the critical avalanche energy to failure as a percentage of the critical Third-Quadrant Safe Operating Area (SOA) energy for the same stress duration. Avalanche stress is comprised of a high voltage with relatively low current while the device conducts by impact ionization, while Third-Quadrant SOA stress is comprised of a high current with low voltage while the device body diode conducts by drift-diffusion. By comparing energy dissipation of the power MOSFET under avalanche with energy dissipation in Third-Quadrant overcurrent conduction, it is possible to determine how well optimised the device is for Unclamped Inductive Switching (UIS). The Third-Quadrant SOA and avalanche ruggedness of SiC MOSFETs is studied using experimental measurements and simulations. A custom junction temperature measurement circuit has been used to estimate the peak junction temperature with the aid of electrothermal simulations. This technique has been applied to Asymmetrical Trench, Planar, and Double Trench SiC MOSFETs, rated at 650 V and with similar on-state resistances. The results show that the ratio of the critical avalanche energy to the SOA energy for 50 mus stress durations is 97% for the Asymmetrical MOSFET, 40% for the Planar MOSFET and 46% for the Double Trench MOSFET, suggesting the Asymmetrical Trench MOSFET is better optimised.
Source: Explore Bristol Research
Institution: University of Warwick
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7222375005