Bit-Accurate FPGA Current Control of a PV-STATCOM: Delay and Word-Length Limits for Ride-Through
Year: 2026
Type: article
Abstract: The sampling-to-update delay and fixed-point word length that a PV-STATCOM current controller can tolerate during ride-through are rarely quantified against ride-through metrics, and complete fixed-point FPGA fast paths are rarely reported with post-route timing. A dq-domain simulation reproduces an exact discrete-time model of the current loop to within 1.2 × 10−6 pu. A stationary-frame co-simulation that runs the bit-accurate fast path, and in 12 cases the VHDL itself in lock step, repeats a 640-case balanced-sag matrix: no case fails at short-circuit ratio (SCR) of 6 or more with 0.5 pu or more retained source voltage (0 of 192), and 116 of 128 fail at SCR of 3 or less with 0.2 pu or less. Selected cases are re-run with dead time, sensor errors, jitter, inductor saturation and single- and two-phase-to-ground faults. Current-step overshoot rises from 0% to 82% as the effective delay grows from 50 to 350 µs. With the full core, 16 fractional bits reproduce the floating-point pass/fail outcome in all 64 averaged-plant cases. A Q12.20 VHDL fast path matches its integer model bit for bit and meets 100 MHz out of context (worst slack +0.219 ns; 6480 LUTs, 65 DSP48E1); the control tick takes 208 clocks (2.08 µs).
Source: Electronics
Author: Ramasamy Srinivasagan
Language: English
Subfield: Control and Systems Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,896
OpenAlex ID: W7223121458