Year: 2026
Type: article
Abstract: Spiking Neural Networks (SNNs) have attracted increasing interest as an energy-efficient computational paradigm inspired by the behavior of biological neurons. However, their efficient implementation in hardware remains challenging due to the diversity of neuron models, encoding schemes, and the substantial hardware resources required for large-scale networks. This thesis presents a scalable and configurable hardware architecture for the implementation of various SNNs as processing units (PUs) on FPGA platforms. The proposed approach is supported by an automated design flow that generates the required HDL description according to the selected network topology and design requirements, thereby guaranteeing compatibility across various FPGA platforms. The proposed architecture is evaluated using both a temporal encoding SNN scheme and a hybrid encoding SNN scheme, demonstrating its ability to accommodate different node structures and network configurations. To demonstrate the scalability of the architecture, both encoding schemes are evaluated on the MNIST classification dataset, achieving an inference accuracy of 91.44%. The hybrid SNN implementation requires approximately twice the hardware resources of the conventional temporal encoding implementation; however, the two implementations differ in several architectural aspects and therefore do not constitute a direct resource comparison. In particular, the hybrid SNN incorporates hardwired weights and does not utilize the node-reuse feedback mechanism available in the complete scalable architecture. Despite its higher resource utilization, the hybrid scheme achieves approximately a tenfold reduction in inference latency. Nevertheless, this comparison considers only computation time, excluding any overhead associated with data transfer and loading. Overall, the presented architecture demonstrates the feasibility of supporting diverse SNN encoding schemes and network topologies through a scalable and automated implementation methodology, applicable to a wide range of FPGA platforms, with potential for adaptation to Application-Specific Integrated Circuit (ASIC) implementations.
Source: Νημερτής
Author: Χατζημιχαήλ, Θεόδωρος
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7223509457