Comparative analysis of memristor models and implementation of a variation-tolerant memristive weighted logic half-adder
Year: 2026
Type: article
Abstract: This article presents a detailed comparative evaluation of three widely referenced memristor model formulations, namely, the Strukov–Williams linear ion-drift model, the Joglekar nonlinear windowing model, and the Voltage-Threshold Adaptive Memristor (VTEAM) model, alongside the physical design and circuit-level validation of a noise-tolerant weighted-logic half-adder. Driven by a continuous 1.0 V, 1.0 Hz sinusoidal drive, baseline mean power dissipation is established to be minimal for the VTEAM formulation, with a mean power consumption to 0.0091 mW (9.1 μ W). To eliminate parasitic sneak-path currents in passive arrays, a 2-Diode 1-Memristor cell configuration is combined with differential transimpedance amplifier (TIA) virtual-ground sensing. Circuit simulations demonstrate that virtual-ground readout suppresses sneak leakage by more than five orders of magnitude relative to signal levels (1.86 μ A signal current vs 10 pA sub-threshold diode saturation floor). The multi-layer weighted-logic half-adder maps continuous synaptic weights W i j ∈ [ − 1.5 , + 1.5 ] into differential conductance pairs bounded within a range from 10–100 μ S. Statistical validation via 1000-trial Monte Carlo simulations confirms high fault tolerance, maintaining 100% logic classification accuracy up to σ = 5 % device variation, 99.55 % ± 1.25 % under σ = 10 % industrial process tolerances (with Mean Absolute Error MAE = 0.01561 V ), and 89.58 % ± 6.42 % under severe σ = 20 % fluctuations.
Source: Engineering Research Express
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W7224007546