Year: 2026
Type: article
Abstract: This work investigates silicon (Si) thinning by wet alkaline etching to enable vertical bit lines (VBL) and monocrystalline silicon Gate-All-Around (GAA) architectures for 3D DRAM integration. Two etchants—tetramethylammonium hydroxide (TMAH) and ammonium hydroxide (NH₄OH)—were systematically studied. Process screening was initially performed on blanket Si to identify conditions offering controlled etch rates and low surface roughness. Optimal conditions were then applied to wagon wheels and 3D patterned test structures, revealing strong anisotropic behaviour influenced by Si crystallography. To mitigate this directional dependence, wafers with a 45° notch rotation were explored to align vertical sidewalls along the <100> orientation, promoting isotropic etching in the desired directions. In TMAH, rotated wafers initially exhibited suppressed lateral etch rates, but prolonged etching exposed fast-etching planes, leading to undesired lateral etching. NH₄OH demonstrated a similar evolution, though boron-doped Si showed partial etch-stop behaviour and increased surface roughness. Blanket etch tests on epitaxially grown boron-doped Si further corroborated these observations. These insights provide critical guidance for integrating scalable GAA devices in next-generation 3D-DRAM architectures.
DOI: 10.4028/p-ec38yh
Institution: IMEC
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7224273936