FPGA Implementation of a RISC-V-Based Neuromorphic Coprocessor SoC.
Year: 2026
Type: preprint
Abstract: Most hardware for neural inference does the same amount of work whether its input is busy or almost empty. Spiking neural networks do not have to: their neurons talk in brief events, so a design can simply skip the inputs that stay silent. We built a small system-on-chip around this idea on a PYNQ Z2 board (Zynq-7020). A five-stage pipelined RV32I processor, written in Verilog, takes an image, turns it into spikes and hands them to a neuromorphic coprocessor of leaky integrate-and-fire (LIF) neurons arranged 64–500–10. The coprocessor only touches the synapses of inputs that actually fired. The processor passes 40 of the 42 rv32ui tests (the other two exercise features it does not have) and all 71 checks of our self-test. On the full 10,000 image MNIST test set, reduced to 8 × 8 pixels, the coprocessor reaches 94.68% accuracy at 50MHz and agrees bit for bit with our software model on every image we checked. It needs 197,770 cycles per image on average, about four times fewer than a dense version of the same network, while using 11,010 LUTs, 943 flip flops and one block RAM. Its cycle count follows a simple formula exactly, and tests with deliberately wrong neuron models confirm that the hardware behaves as intended.
Authors: Naik, Saniya, Singh, Balwant Kr
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7224874527