Year: 2026
Type: article
Abstract: Multi-chip paralleled silicon carbide (SiC) MOSFET power modules require package layouts that control both switching-induced source feedback and chip-level heat-flow nonuniformity. This paper presented an electrothermal layout design method for a 1200 V, 450 A double-sided-cooled module that combined die screening, branch-level source-feedback analysis, and chip-spacing optimization. The electrical model retained self and mutual inductances and used the equivalent feedback inductance L fb to assess layout-dependent source feedback. Switching simulations showed the relationship between L fb mismatch and transient current imbalance, with different current slew rates in the parallel branches. A thermal-resistance matrix and a temperature-uniformity index guided the chip-spacing selection. Under the investigated conditions, the selected layout reduced the simulated nonuniformity index from 10.07% to 8.68%, with a 2.13 ∘ C increase in the maximum junction temperature. Self-heating and coupling thermal resistances varied little across the tested power distributions, while sensitivity analysis identified the cooling condition as the main influence on peak temperature and temperature spread. Double-pulse tests at 25 ∘ C and 175 ∘ C and dual-interface thermal measurements were performed on the fabricated module. The de-embedded commutation-loop inductance was 4.22 nH, close to the extracted value of 4.05 nH, and measured layer-level thermal resistances agreed with simulation within 6.45%. These results support a layout design approach that considers source-feedback differences, temperature uniformity, and peak junction temperature together.
Source: Results in Engineering
Institution: Fudan University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $1,940
OpenAlex ID: W7206206243