Design and implementation of fault tolerant Network on chip (noc)router
Year: 2026
Type: article
Abstract: This project presents Aether-FTNoC, a 5-port fault-tolerant Network-on-Chip router designed in synthesizable Verilog and implemented in SCL 180 nm CMOS using the Cadence digital design flow. The router protects inter-chip links with single-cycle SECDED Hamming (39,32) error correction, end-to-end CRC-16 integrity checking, adaptive deflection routing around failed links, dual virtual-channel FIFO buffers, and a hardware anti-deadlock watchdog. Functional verification in Cadence Incisive achieved 96.55% code coverage. Logic synthesis in Cadence Genus closed timing at 66.7 MHz with zero violations across 5,448 standard cells. Formal equivalence was proven at 100% using Cadence Conformal LEC. Physical implementation in Cadence Innovus and signoff timing in Cadence Tempus confirmed a clean, tape-out-ready layout. The design adds only 18.45% area over an unprotected baseline, compared to over 200% for traditional triple modular redundancy. About 120 words. Want it shorter, simpler, or in a different style — for example, plain English for a general audience?
Authors: Mrs. Priscilla Sophia P, Rethika S
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7225042514