Work

VexRiscv: A Configurable RISC-V Architecture and VexRiscv_Min on Tang Nano 20K

Year: 2026

Type: article

Abstract: This article presents the organization of VexRiscv, a configurable 32-bit RISC-V core, itshardware generation with SpinalHDL, pipeline and interface options, memory-subsystem configurationsand integration with LiteX. A separate case study examines the operational factory SoC on a Sipeed TangNano 20K through its UART boot log. Direct observations, claims supported by project sources, andproperties requiring further verification are kept distinct.

Source: Zenodo (CERN European Organization for Nuclear Research)

DOI: 10.5281/zenodo.23991096

Author: Malachevsky, A.A.

Language: English

Topic: Embedded Systems Design Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W7225335695

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