A Low-Cost Multi-Modal Sensing-and-Telemetry Testbed for ISAC Proof-of-Concept Studies: Hardware Design, Firmware, and Simulation-Based Evaluation
Year: 2026
Type: preprint
Abstract: Integrated Sensing and Communication (ISAC) is a foundational technology for sixth-generation (6G) wireless networks, yet experimental hardware validation remains constrained by the high cost of Software-Defined Radios (SDRs). This paper presents the design, firmware architecture, hardware implementation, and evaluation of an open-source, dual-node physical layer testbed for ISAC proof-of-concept studies built with off-the-shelf ESP32 microcontrollers and LoRa radio modules. The setup features a stationary hub integrating ultrasonic ranging, interrupt-driven passive infrared (PIR) motion sensing, GPS positional logging, and a sub-GHz Grove-LoRa telemetry link to monitor a mobile, wearable target node. We detail the deterministic FreeRTOS dual-core task allocation, logic-level voltage protection circuits, edge-fusion data reduction efficiency, and a literature-calibrated simulation model evaluating packet delivery ratio, latency, and dynamic shadow fading. Complete circuit schematics, pin-level netlists, firmware, and an itemized $81 Bill of Materials are provided to serve as an accessible, reproducible baseline for early-stage ISAC research and education.
Author: MAYANK SETHIA
Language: English
Subfield: Aerospace Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W7225656859
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