Jpeg-ls Parallelization on Fpga: Splitting Strategies and Core/frequency Selection
Year: 2026
Type: article
Abstract: This paper proposes and benchmarks three spatial partitioning strategies – Horizontal, Vertical, and Block-based – for a multi-core JPEG-LS encoder targeting the Artix-7 FPGA and introduces a new method for selecting the required number of encoder cores and the operating clock frequency from first principles. The method derives both parameters directly from the scanner pixel rate, making core-count selection independent of pixel bit depth. Because a one-pixel-per-clock LOCO-I core closes timing at about 53 MHz on the Artix-7, the method sizes the design at the device-achievable clock rather than an idealized one: for the Sich-3O pixel rate P = 518 Mpix/s the rule N = P / F yields twelve lanes at 45 MHz, a configuration that was synthesized and timing-closed (worst negative slack +0.65 ns) at 540 Mpix/s ≈ 4.32 Gbit/s, meeting the 4.15 Gbit/s requirement; the same design reaches 853 Mpix/s ≈ 6.83 Gbit/s at the 53.3 MHz device fmax. Core count is independent of pixel bit depth, so this sizing holds for 8-, 12-, and 16-bit payloads. All results are taken from post-route implementation reports and compared with commercial and academic implementations.
Source: Komp'ûternì sistemi ta merežì
Authors: T. L. Hrytsko, V. S. Hlukhov
Institution: Lviv Polytechnic National University
Language: English
Subfield: Computer Vision and Pattern Recognition
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7225805444