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Norio Masui

Observed name: N. Masui
Observed institution: Renesas Electronics (Japan)
OpenAlex ID: A5000502435
A 600-MHz Single-Chip Multiprocessor With 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal Memory
2004 · S. Kaneko, H. Kondo, et al. · IEEE Journal of Solid-State Circuits · 35
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors
2008 · Hiroyuki Kondo, Mamoru Sakugawa, et al. · IEEE Journal of Solid-State Circuits · 25
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications
2009 · Hiroyuki Kondo, Sugako Otani, et al. · IEEE Journal of Solid-State Circuits · 13
Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors
2007 · Masami Nakajima, Hiroyuki Kondo, et al. · Symposium on VLSI Circuits · 7
A 600 MHz single-chip multiprocessor with 4.8 GB/s internal shared pipelined bus and 512 kB internal memory
2003 · S. Kaneko, K. Sawai, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 7
Heterogeneous multicore SoC for secure multimedia applications
2008 · Hiroyuki Kondo, Masami Nakajima, et al. · Custom Integrated Circuits Conference · 1
1.047GHz, 1.2V, 90nm CMOS, 2-Way VLIW DSP Core Using Saturation Anticipator Circuit
2006 · H. Suzuki, H. Takata, et al. · Symposium on VLSI Circuits · 1
Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors
2007 · Masami Nakajima, Koichi Ishimi, et al. · Technical report of IEICE. SDM
Works count: 8
Citation count: 89
H-index: 5
I10-index: 3
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