Get started
Author

Grigorios Magklis

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling
2004 · G. Semeraro, G. Magklis, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 367
The ARM Scalable Vector Extension
2017 · Nigel Stephens, Stuart Biles, et al. · IEEE Micro · 330
PDF
Dynamically tuning processor resources with adaptive processing
2003 · D.H. Albonesi, R. Balasubramonian, et al. · Computer · 159
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
2003 · Grigorios Magklis, Michael L. Scott, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 149
PDF
Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture
2002 · Greg Semeraro, Steven Dropsho, et al. · 145
Understanding the Thermal Implications of Multi-Core Architectures
2007 · Pedro Chaparro, José Gonzáles, et al. · IEEE Transactions on Parallel and Distributed Systems · 127
Integrating adaptive on-chip storage structures for reduced dynamic power
2002 · S. Dropsho, Alper Buyuktosunoglu, et al. · 117
Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor
2003 · G. Magklis, G. Semeraro, et al. · IEEE Micro · 106
PDF
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
2008 · Qiong Cai, José González, et al. · International Conference on Parallel Architectures and Compilation Techniques (PACT) · 90
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
2003 · G. Semeraro, D.H. Albonesi, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 77
A Dynamically Adaptable Hardware Transactional Memory
2010 · Marc Lupon, Grigorios Magklis, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 57
FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery
2009 · Marc Lupon, Grigorios Magklis, et al. · International Conference on Parallel Architectures and Compilation Techniques (PACT) · 53
Integrating adaptive on-chip storage structures for reduced dynamic power
2003 · S. Dropsho, A. Buyuktosunoglu, et al. · International Conference on Parallel Architectures and Compilation Techniques (PACT) · 52
Processor Microarchitecture: An Implementation Perspective
2010 · Antonio González, Fernando Latorre, et al. · Synthesis lectures on computer architecture · 43
Distributing the Frontend for Temperature Reduction
2005 · P. Chaparro, G. Magklis, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 41
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
2003 · Grigorios Magklis, Michael L. Scott, et al. · ACM SIGARCH Computer Architecture News · 36
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
2003 · Grigorios Magklis, Michael L. Scott, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 32
Hiding synchronization delays in a GALS processor microarchitecture
2004 · G. Semeraro, D.H. Albonesi, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 30
Thread shuffling: Combining DVFS and thread migration to reduce energy consumptions for multi-core systems
2011 · Qiong Cai, Jose Gonzalez, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 26
Independent Front-end and Back-end Dynamic Voltage Scaling for a GALS Microarchitecture
2006 · Grigorios Magklis, Pedro Chaparro, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 25
Dynamically Trading Frequency for Complexity in a GALS Microprocessor
2005 · S. Dropsho, G. Semeraro, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 25
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip
2021 · Dave Ditzel, Roger Espasa, et al. · IEEE Hot Chips Symposium · 24
Version management alternatives for hardware transactional memory
2008 · Marc Lupon, Grigorios Magklis, et al. · Memory Performance: Dealing With Applications, Systems And Architecture · 16
The Energy Impact of Aggressive Loop Fusion
· Yongkang Zhu, Grigorios Magklis, et al. · UR Research (University of Rochester) · 15
PDF
Speculative hardware/software co-designed floating-point multiply-add fusion
2014 · Marc Lupon, Enric Gibert, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 14
Works count: 59
Citation count: 2,241
H-index: 22
I10-index: 28
Year
Topic
Type