Author

Srikanth Arekapudi

Observed names: S Arekapudi, S. Arekapudi

Observed institutions: University of Massachusetts Amherst, Advanced Micro Devices (United States), Stanford SystemX Alliance, Stanford University

OpenAlex ID: A5005400568

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

2012 · Visvesh S. Sathe, Srikanth Arekapudi, et al. · IEEE Journal of Solid-State Circuits · 68

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU

2011 · T Fischer, S Arekapudi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47

Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS

2011 · Hugh McIntyre, Srikanth Arekapudi, et al. · IEEE Journal of Solid-State Circuits · 35

40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86–64 core

2011 · M Golden, S Arekapudi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 26

Carrizo: A High Performance, Energy Efficient 28 nm APU

2015 · Benjamin Munger, David Akeson, et al. · IEEE Journal of Solid-State Circuits · 19

A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support

2006 · M. Golden, S. Arekapudi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19

Resonant clock design for a power-efficient high-volume x86–64 microprocessor

2012 · Visvesh Sathe, Srikanth Arekapudi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11

A Low-Power Distributed Wide-Band LNA in 0.18μM CMOS

2005 · S. Arekapudi, E. Iroaga, et al. · IEEE International Symposium on Circuits and Systems proceedings · 8

Using Hardware to Configure a Load-Balanced Switch

2005 · S. Arekapudi, Shang-Tse Chuang, et al. · IEEE Micro · 4

Configuring a load-balanced switch in hardware

2005 · S. Arekapudi, Shang-Tse Chuang, et al. · IEEE Symposium on High-Performance Interconnects (HOTI) · 3

Test pattern generation for timing-induced functional errors in hardware-software systems

2002 · S. Arekapudi, Fei Xin, et al. · Proceedings · 3

ATPG for timing-induced functional errors on trigger events in hardware-software systems

2003 · S. Arekapudi, Fei Xin, et al. · IEEE European Test Symposium (ETS) · 2

DDR2 Memory Support

2006 · Michael Golden, Srikanth Arekapudi, et al.

ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems

2003 · Srikanth Arekapudi, Fei Xin, et al. · Journal of Circuits Systems and Computers

Works count: 17

Citation count: 245

H-index: 8

I10-index: 7