Get started
Author

Julian Oppermann

Observed names: J. Oppermann, Oppermann, Julian
ORCID: 0000-0002-8073-720X
Observed ORCID: 0000-0002-8073-720X
OpenAlex ID: A5010007635
ILP-based modulo scheduling for high-level synthesis
2016 · Julian Oppermann, Andreas Koch, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 31
Hardware/software co-compilation with the Nymble system
2013 · Jens Huthmann, Bjorn Liebig, et al. · International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) · 30
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors
2022 · Mihaela Damian, Julian Oppermann, et al. · ACM/IEEE Design Automation Conference (DAC) · 26
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators
2018 · Lukas Sommer, Julian Oppermann, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 26
Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language
2024 · Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 21
Exact and Practical Modulo Scheduling for High-Level Synthesis
2019 · Julian Oppermann, Melanie Reuter-Oppermann, et al. · ACM Transactions on Reconfigurable Technology and Systems · 13
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling
2019 · Julian Oppermann, Patrick Sittel, et al. · Lecture notes in computer science · 12
PDF
ILP-Based Modulo Scheduling and Binding for Register Minimization
2018 · Patrick Sittel, Martin Kumm, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 12
Automatic high-level synthesis of multi-threaded hardware accelerators
2014 · Jens Huthmann, Julian Oppermann, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 11
Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs
2019 · Lukas Weber, Lukas Sommer, et al. · International Conference on Field-Programmable Technology (FPT) · 10
NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management
2018 · Vincon, Tobias, Hardock, Sergej, et al. · Reutlingen University Academic Bibliography (Reutlingen University) · 10
PDF
Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs
2023 · Christoph Weckert, Leonardo Solis-Vasquez, et al. · International Conference for High Performance Computing, Networking, Storage and Analysis (SC) · 8
PDF
Experiences Building an MLIR-Based SYCL Compiler
2024 · Ettore Tiotto, Víctor Pérez, et al. · Proceedings of the CGO/Proceedings of the ... CGO · 7
PDF
The Scale4Edge RISC-V Ecosystem
2022 · Wolfgang Ecker, Peer Adelt, et al. · Design, Automation, and Test in Europe · 6
SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis
2019 · Julian Oppermann, Lukas Sommer, et al. · International Conference on Field-Programmable Technology (FPT) · 6
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators
2015 · Julian Oppermann, Andreas Koch, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 6
Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis
2018 · Julian Oppermann, Melanie Reuter-Oppermann, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 5
Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models
2015 · Ting Yu, Julian Oppermann, et al. · Concurrency and Computation Practice and Experience · 5
PDF
Synthesis of interleaved multithreaded accelerators from OpenMP loops
2017 · Lukas Sommer, Julian Oppermann, et al. · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 4
Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis
2016 · Julian Oppermann, Andreas Koch · IEEE Smart World Congress and International Conferences on Ubiquitous Intelligence & Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People (SmartWorld/UIC/ATC/ScalCom/CBDCom/IoP) · 4
Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs
2022 · Hanna Kruppe, Lukas Sommer, et al. · Lecture notes in computer science · 3
High-performance computing for SKA transient search: Use of FPGA-based accelerators
2023 · R. Aafreen, R. Abhishek, et al. · Journal of Astrophysics and Astronomy · 2
PDF
Pulsar search acceleration using FPGAs and OpenCL templates
2023 · Julian Oppermann, Mitchell B. Mickaliger, et al. · Experimental Astronomy · 1
PDF
Advances in ILP-based Modulo Scheduling for High-Level Synthesis
2019 · Oppermann, Julian · Technischen Universität Darmstadt · 1
GeMS: a generator for modulo scheduling problems: work in progress
2018 · Julian Oppermann, Sebastian Vollbrecht, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 1
Works count: 34
Citation count: 264
H-index: 10
I10-index: 11
Year
Topic
Type