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Pai-Yu Chen
Observed institutions:
National Taiwan University,
National Tsing Hua University,
Arizona State University,
The University of Texas at Austin
ORCID:
0000-0002-9146-2192
Observed ORCID:
0000-0002-9146-2192
OpenAlex ID:
A5011351663
SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations
2018
·
Shinhyun Choi
, Scott H. Tan
, et al.
·
Nature Materials
·
689
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
2018
·
Pai-Yu Chen
, Xiaochen Peng
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
653
Ferroelectric FET analog synapse for acceleration of deep neural network training
2017
·
Matthew Jerry
, Pai-Yu Chen
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
597
Emerging Memory Technologies: Recent Trends and Prospects
2016
·
Shimeng Yu
, Pai-Yu Chen
·
IEEE Solid-State Circuits Magazine
·
555
NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures
2017
·
Pai-Yu Chen
, Xiaochen Peng
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
447
Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design
2015
·
Pai-Yu Chen
, Shimeng Yu
·
IEEE Transactions on Electron Devices
·
364
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
2015
·
Pai-Yu Chen
, Binbin Lin
, et al.
·
291
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
2018
·
Win-San Khwa
, Jia-Jing Chen
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
260
Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect
2015
·
Shimeng Yu
, Pai-Yu Chen
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
222
Binary neural network with 16 Mb RRAM macro chip for classification and online training
2016
·
Shimeng Yu
, Zhiwei Li
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
218
MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
2017
·
Lixue Xia
, Boxun Li
, et al.
·
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
·
186
NbOx based oscillation neuron for neuromorphic computing
2017
·
Ligang Gao
, Pai-Yu Chen
, et al.
·
Applied Physics Letters
·
160
Device and materials requirements for neuromorphic computing
2018
·
Raisul Islam
, Haitong Li
, et al.
·
Journal of Physics D Applied Physics
·
158
A ferroelectric field effect transistor based synaptic weight cell
2018
·
Matthew Jerry
, Sourav Dutta
, et al.
·
Journal of Physics D Applied Physics
·
146
Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array
2016
·
Ligang Gao
, Pai-Yu Chen
, et al.
·
IEEE Electron Device Letters
·
146
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
2015
·
Ligang Gao
, I-Ting Wang
, et al.
·
Nanotechnology
·
141
PDF
Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories
2015
·
Ligang Gao
, Pai-Yu Chen
, et al.
·
IEEE Electron Device Letters
·
100
Understanding the resistive switching characteristics and mechanism in active SiOx-based resistive switching memory
2012
·
Yao-Feng Chang
, Pai-Yu Chen
, et al.
·
Journal of Applied Physics
·
83
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons
2018
·
Xiaoyu Sun
, Xiaochen Peng
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
80
MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
2016
·
Lixue Xia
, Boxun Li
, et al.
·
Design, Automation, and Test in Europe
·
75
Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array
2016
·
Ligang Gao
, Pai-Yu Chen
, et al.
·
IEEE Transactions on Electron Devices
·
74
Technology-design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip
2015
·
Pai-Yu Chen
, Deepak Kadetotad
, et al.
·
Design, Automation, and Test in Europe
·
74
Electroforming and resistive switching in silicon dioxide resistive memory devices
2015
·
Burt W. Fowler
, Yao-Feng Chang
, et al.
·
RSC Advances
·
73
Design of Ternary Neural Network With 3-D Vertical RRAM Array
2017
·
Zhiwei Li
, Pai-Yu Chen
, et al.
·
IEEE Transactions on Electron Devices
·
70
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration
2015
·
Deepak Kadetotad
, Zihan Xu
, et al.
·
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
·
63
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Works count:
67
Citation count:
6,606
H-index:
35
I10-index:
49
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