Author

Nur A. Touba

Observed names: N. A. Touba, N.A Touba, N.A. Touba, Nur Touba, Touba, Nur

Institution: The University of Texas at Austin

Observed institutions: Texas Tech University, University of Potsdam, The University of Texas at Austin, Stanford University

ORCID: 0000-0001-5083-6701

Observed ORCID: 0000-0001-5083-6701

OpenAlex ID: A5012356472

Survey of Test Vector Compression Techniques

2006 · N.A. Touba · IEEE Design & Test of Computers · 439

Static compaction techniques to control scan vector power dissipation

2002 · R. Sankaralingam, R.R. Oruganti, et al. · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 354

An efficient test vector compression scheme using selective huffman coding

2003 · A. Jas, J. Ghosh-Dastidar, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 277

Test vector decompression via cyclical scan chains and its application to testing core-based designs

2002 · A. Jas, N.A. Touba · Proceedings/Proceedings - International Test Conference · 275

Cost-effective approach for reducing soft error failure rate in logic circuits

2004 · K. Mohanram, N.A. Touba · 271

Scan vector compression/decompression using statistical coding

2003 · A. Jas, J. Ghosh-Dastidar, et al. · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 264

Test vector encoding using partial LFSR reseeding

2002 · C.V. Krishna, A. Jas, et al. · Proceedings/Proceedings - International Test Conference · 230

Altering a pseudo-random bit sequence for scan-based BIST

2002 · N.A. Touba, E.J. McCluskey · 191

Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code

2007 · Avijit Dutta, Nur A. Touba · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 178

Reducing test data volume using LFSR reseeding with seed compression

2003 · C.V. Krishna, N.A. Touba · Proceedings/Proceedings - International Test Conference · 166

Reducing power dissipation during test using scan chain disable

2002 · R. Sankaralingam, B. Pouya, et al. · 149

Logic synthesis of multilevel circuits with concurrent error detection

1997 · N.A. Touba, E.J. McCluskey · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 148

System-on-Chip Test Architectures: Nanometer Design for Testability

2007 · Laung‐Terng Wang, Charles E. Stroud, et al. · 133

Test point insertion based on path tracing

2002 · N.A. Touba, E.J. McCluskey · 125

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes

1999 · Debaleena Das, Nur A. Touba · Journal of Electronic Testing · 125

Reducing test data volume using external/LBIST hybrid test patterns

2002 · D. Das, N.A. Touba · Proceedings/Proceedings - International Test Conference · 113

Controlling peak power during scan testing

2003 · R. Sankaralingam, N.A. Touba · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 111

Improving logic obfuscation via logic cone analysis

2015 · Yu-Wei Lee, Nur A. Touba · 109

Test data compression using dictionaries with selective entries and fixed-length indices

2003 · Lei Li, Krishnendu Chakrabarty, et al. · ACM Transactions on Design Automation of Electronic Systems · 103

LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test

2007 · Jinkyu Lee, Nur A. Touba · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 102

Partial error masking to reduce soft error failure rate in logic circuits

2004 · K. Mohanram, N.A. Touba · Proceedings/Proceedings - Symposium on Computer Arithmetic · 96

Virtual scan chains: a means for reducing scan length in cores

2002 · A. Jas, B. Pouya, et al. · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 94

Bit-fixing in pseudorandom sequences for scan BIST

2001 · N.A. Touba, E.J. McCluskey · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 94

Testing embedded cores using partial isolation rings

2002 · N.A. Touba, B. Pouya · Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium · 92

Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST

2002 · N.A. Touba, E.J. McCluskey · Proceedings/Proceedings - International Test Conference · 88

Works count: 245

Citation count: 7,011

H-index: 44

I10-index: 105