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Vincent De Heyn

Observed names: Heyn, M. de, V De Heyn, V. De Heyn, V. de Heyn, V.De Heyn, Vincent Heyn, Vincent de Heyn
Institution: IMEC
OpenAlex ID: A5021458154
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation
2005 · J. Ryckaert, C. Desset, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 225
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a
2007 · Julien Ryckaert, Geert Van der Plas, et al. · IEEE Journal of Solid-State Circuits · 107
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication
2007 · Julien Ryckaert, Marian Verhelst, et al. · IEEE Journal of Solid-State Circuits · 71
First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs
2018 · E. Capogreco, L. Witters, et al. · IEEE Transactions on Electron Devices · 63
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18/spl mu/m CMOS
2006 · J. Ryckaert, M. Badaroglu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 59
Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition
2017 · L. Witters, H. Arimura, et al. · IEEE Transactions on Electron Devices · 57
Characterization and modeling of transient device behavior under CDM ESD stress
2004 · J. Willemen, A. Andreini, et al. · Journal of Electrostatics · 55
The Potential of FinFETs for Analog and RF Circuit Applications
2007 · Piet Wambacq, Bob Verbruggen, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 53
Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage
2002 · V. De Heyn, G. Groeseneken, et al. · IEEE International Reliability Physics Symposium proceedings · 51
Influence of gate length on ESD-performance for deep sub micron CMOS technology
2003 · K. Bock, B. Keppens, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 39
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
2018 · A. Vandooren, J. Franco, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 32
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a
2007 · Julien Ryckaert, Geert van der Plas, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 31
Carrier-Based UWB Impulse Radio: Simplicity, Flexibility, and Pulser Implementation in 0.18-micron CMOS
2006 · J. Ryckaert, M. Badaroglu, et al. · IEEE International Conference on Ultra-Wideband (ICUWB) · 29
3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
2018 · A. Vandooren, J. Franco, et al. · Symposium on VLSI Technology · 28
BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration
2018 · J. Franco, Z. Wu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27
A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS
2007 · Vincent De Heyn, Geert Van der Plas, et al. · European Solid-State Circuits Conference (ESSCIRC) · 25
Suitability of FinFET technology for low-power mixed-signal applications
2006 · B. Parvais, C. Gustin, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 21
Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability
2017 · H. Arimura, L. Witters, et al. · Symposium on VLSI Technology · 18
3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
2018 · A. Vandooren, J. Franco, et al. · IEEE Transactions on Electron Devices · 17
Contributions to standardization of Transmission Line Pulse testing methodology
2001 · B. Keppens, V. De Heyn, et al. · Electrical Overstress/Electrostatic Discharge Symposium · 17
Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition
2017 · L. Witters, F. Sebaai, et al. · Symposium on VLSI Technology · 16
Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain
2004 · D. Linten, S. Thijs, et al. · IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) · 15
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
2018 · A. Vandooren, L. Witters, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 14
High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG
2019 · E. Capogreco, H. Arimura, et al. · Symposium on VLSI Technology · 13
Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O stages
2003 · Stadler, W., Esmark, K., et al. · Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft) · 13
Works count: 51
Citation count: 1,224
H-index: 18
I10-index: 31
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