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Takayuki Shibasaki

Observed names: T. Shibasaki, Takayuki SHIBASAKI, 崇之 柴崎
Institution: Fujitsu (Japan)
OpenAlex ID: A5022697142
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications
2020 · Satoshi Matsubara, Motomu Takatsu, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 176
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS
2016 · Takayuki Shibasaki, Takumi Danjo, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 78
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
2017 · Wahid Rahman, Danny Yoo, et al. · IEEE Journal of Solid-State Circuits · 67
A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS
2010 · Keita Takatsu, Hirotaka Tamura, et al. · Custom Integrated Circuits Conference · 40
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS
2014 · Takayuki Shibasaki, Win Chaivipas, et al. · Symposium on VLSI Circuits · 34
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range
2008 · Takayuki Shibasaki, Hirotaka Tamura, et al. · IEEE Journal of Solid-State Circuits · 29
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS
2009 · Kouichi Kanda, Hirotaka Tamura, et al. · IEEE Journal of Solid-State Circuits · 24
6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
2019 · Danny Yoo, Mohammad Bagherbeik, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 22
A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS
2019 · Danny Yoo, Mohammad Bagherbeik, et al. · IEEE Solid-State Circuits Letters · 20
6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS
2017 · Wahid Rahman, Danny Yoo, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 20
A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS
2010 · Nikola Nedovic, Anders Kristensson, et al. · IEEE Journal of Solid-State Circuits · 20
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS
2013 · Y. Doi, T. Shibasaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 17
24 to 34-Gb/s ×4 Multi-Rate VCSEL-Based Optical Transceiver with Referenceless CDR
2016 · Yukito Tsunoda, Takayuki Shibasaki, et al. · Optical Fiber Communication Conference · 13
25.78-Gb/s VCSEL-Based Optical Transceiver with Retimer-embedded Driver and Receiver ICs
2015 · Yukito Tsunoda, Takayuki Shibasaki, et al. · Optical Fiber Communication Conference · 13
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS
2009 · K. Kanda, H. Tamura, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
2013 · Yoshiyasu Doi, Takayuki Shibasaki, et al. · IEEE Journal of Solid-State Circuits · 11
A Decomposition Method for Makespan Minimization in Job-Shop Scheduling Problem Using Ising Machine
2021 · Daichi Shimada, Toshiyuki Shibuya, et al. · IEEE International Conference on Industrial Engineering and Applications (ICIEA) · 10
A 20-GHz Injection-Locked LC Divider with a 25-% Locking Range
2006 · T. Shibasaki, H. Tamura, et al. · Symposium on VLSI Circuits · 10
A 30Gb/s 2x Half-Baud-Rate CDR
2019 · Danny Yoo, Mohammad Bagherbeik, et al. · Custom Integrated Circuits Conference · 8
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS
2015 · Yukito Tsunoda, Takayuki Shibasaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4
32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS
2013 · Yoshiyasu Doi, Takayuki Shibasaki, et al. · IEICE Technical Report; IEICE Tech. Rep. · 4
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS
2016 · Hiroki Miyaoka, Futoshi Terasawa, et al. · Symposium on VLSI Circuits · 3
A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology
2009 · Nikola Nedovic, Samir Parikh, et al. · Symposium on VLSI Circuits · 3
A 56-Gb/s Wireline Transceiver in 20nm CMOS
2015 · Takayuki Shibasaki, Yanfei Chen, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 2
22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS
2015 · Takayuki Shibasaki, Yukito Tsunoda, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2
Works count: 45
Citation count: 644
H-index: 13
I10-index: 18
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