Author

Angshuman Parashar

Observed name: Parashar, Angshuman

Observed institutions: Nvidia (United Kingdom), Georgia Institute of Technology, Pennsylvania State University, Intel (United States), Nvidia (United States), Intel (Malaysia), Indian Institute of Technology Delhi

ORCID: 0000-0001-9936-6501

Observed ORCID: 0000-0001-9936-6501

OpenAlex ID: A5024901904

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

2017 · Angshuman Parashar, Minsoo Rhu, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 928

Timeloop: A Systematic Approach to DNN Accelerator Evaluation

2019 · Angshuman Parashar, Priyanka Raina, et al. · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · 644

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

2017 · Angshuman Parashar, Minsoo Rhu, et al. · ACM SIGARCH Computer Architecture News · 590

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Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach

2019 · Hyoukjun Kwon, Prasanth Chatarasi, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 327

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings

2020 · Hyoukjun Kwon, Prasanth Chatarasi, et al. · IEEE Micro · 232

Triggered instructions: a control paradigm for spatially-programmed architectures

2013 · Angshuman Parashar, Michael Pellauer, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 120

Mind mappings: enabling efficient algorithm-accelerator mapping space search

2021 · Kartik Hegde, Po-An Tsai, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 104

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HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing

2011 · Michael Pellauer, Michael Adler, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 104

Leap scratchpads: automatic memory and cache management for reconfigurable logic

2011 · Michael Adler, Kermin E. Fleming, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 94

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling

2022 · Yannan Nellie Wu, Po-An Tsai, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 92

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Mechanisms for bounding vulnerabilities of processor structures

2007 · Niranjan Kumar Soundararajan, Angshuman Parashar, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 60

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy

2004 · Angshuman Parashar, Sudhanva Gurumurthi, et al. · ACM SIGARCH Computer Architecture News · 50

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity

2023 · Yannan Nellie Wu, Po-An Tsai, et al. · IEEE/ACM International Symposium on Microarchitecture (MICRO) · 48

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Triggered instructions: a control paradigm for spatially-programmed architectures

2013 · Angshuman Parashar, Michael Pellauer, et al. · ACM SIGARCH Computer Architecture News · 46

SlicK: slice-based locality exploitation for efficient redundant multithreading

2006 · Angshuman Parashar, Anand Sivasubramaniam, et al. · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 46

Leveraging latency-insensitivity to ease multiple FPGA design

2012 · Kermin Elliott Fleming, Michael Adler, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 36

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators

2021 · Prasanth Chatarasi, Hyoukjun Kwon, et al. · ACM Transactions on Architecture and Code Optimization · 35

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Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO

2018 · Kwon, Hyoukjun, Chatarasi, Prasanth, et al. · arXiv (Cornell University) · 34

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DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators

2022 · Sheng-Chun Kao, Michael Pellauer, et al. · Design, Automation, and Test in Europe · 30

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Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators

2020 · Chatarasi, Prasanth, Kwon, Hyoukjun, et al. · arXiv (Cornell University) · 26

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Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators

2021 · Yannan Nellie Wu, Po-An Tsai, et al. · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · 23

Flexion: A Quantitative Metric for Flexibility in DNN Accelerators

2020 · Hyoukjun Kwon, Michael Pellauer, et al. · IEEE Computer Architecture Letters · 22

Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms

2024 · Qijing Huang, Po-An Tsai, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 20

Data Orchestration in Deep Learning Accelerators

2020 · Tushar Krishna, Hyoukjun Kwon, et al. · Synthesis lectures on computer architecture · 19

Efficient Spatial Processing Element Control via Triggered Instructions

2014 · Angshuman Parashar, Michael Pellauer, et al. · IEEE Micro · 18

Works count: 60

Citation count: 3,879

H-index: 22

I10-index: 32