Author

Chen-Han Ho

Institution: University of Wisconsin–Madison

Observed institution: University of Wisconsin–Madison

OpenAlex ID: A5032872832

DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing

2012 · Venkatraman Govindaraju, Chen-Han Ho, et al. · IEEE Micro · 259

Dynamically Specialized Datapaths for energy efficient computing

2011 · Venkatraman Govindaraju, Chen-Han Ho, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 209

Enabling GPGPU Low-Level Hardware Explorations with MIAOW

2015 · Raghuraman Balasubramanian, Vinay Gangadhar, et al. · ACM Transactions on Architecture and Code Optimization · 60

PDF

Sampling + DMR

2011 · Shuou Nomura, Matthew D. Sinclair, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 48

Design, integration and implementation of the DySER hardware accelerator into OpenSPARC

2012 · Jesse Benson, Ryan Cofell, et al. · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 47

Architectural Simulators Considered Harmful

2015 · Tony Nowatzki, Jaikrishnan Menon, et al. · IEEE Micro · 44

Efficient execution of memory access phases using dataflow specialization

2015 · Chen-Han Ho, Sung Jin Kim, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 34

MIAOW - An open source RTL implementation of a GPGPU

2015 · Raghuraman Balasubramanian, Vinay Gangadhar, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 26

Sampling + DMR

2011 · Shuou Nomura, Matthew D. Sinclair, et al. · ACM SIGARCH Computer Architecture News · 12

Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing

2012 · Chen-Han Ho, Marc de Kruijf, et al. · Proceedings of the International Conference on Parallel Processing · 7

Efficient execution of memory access phases using dataflow specialization

2015 · Chen-Han Ho, Sung Jin Kim, et al. · ACM SIGARCH Computer Architecture News · 4

OpenSPLySER: The Integrated OpenSPARC and DySER Design

2011 · Jesse Benson, Ryan Cofell, et al. · Minds at UW (University of Wisconsin) · 2

PDF

Prototyping the DySER specialization architecture with OpenSPARC

2012 · Jesse Benson, Ryan Cofell, et al. · IEEE Hot Chips Symposium · 1

Mechanisms for Parallelism Specialization for the DySER Architecture

2012 · Karthikeyan Sankaralingam, Tony Nowatzki, et al. · Minds at UW (University of Wisconsin) · 1

PDF

Design and Evaluation of Dynamically Specialized Datapaths with the DySER Architecture

2010 · Venkatraman Govindaraju, Chen-Han Ho, et al. · Minds at UW (University of Wisconsin) · 1

PDF

Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow

2016 · Chen-Han Ho, Sung Jin Kim, et al. · IEEE Micro

Memory Access Dataflow

2014 · Karthikeyan Sankaralingam, Sung Jin Kim, et al. · Minds at UW (University of Wisconsin)

PDF

Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities

2011 · Chen-Han Ho, Garret Staus, et al. · IEEE Computer Architecture Letters

Dynamical Synthesized Execution Resources (DySER) Deisgn Specification

2010 · Chen-Han Ho · Minds at UW (University of Wisconsin)

PDF

Is It Possible to Fairly Compare Interconnection Networks

1994 · J. Duato, Chen-Han Ho, et al. · International Conference on Parallel and Distributed Systems

Works count: 20

Citation count: 755

H-index: 9

I10-index: 9