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R. Seshasayanan

Leading one detectors and leading one position detectors - An evolutionary design methodology
2013 · K. Kunaraj, R. Seshasayanan · Canadian Journal of Electrical and Computer Engineering · 29
Implementation of computation-reduced DCT using a novel method
2015 · K. K. Senthilkumar, K. Kunaraj, et al. · EURASIP Journal on Image and Video Processing · 26
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Performance of Dual-Polarized DSTTD-IDMA system over correlated frequency selective channels
2014 · K.S. Vishvaksenan, R. Seshasayanan, et al. · Computers & Electrical Engineering · 21
A low-complexity DCT approximation for image compression with 14 additions only
2013 · D. Vaithiyanathan, R. Seshasayanan, et al. · International Conference on Green Computing, Communication and Conservation of Energy · 20
High performance ACS for Viterbi decoder using pipeline T-Algorithm
2015 · D. Vaithiyanathan, J. Nargis, et al. · Alexandria Engineering Journal · 19
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An Evolved Wavelet Library Based on Genetic Algorithm
2014 · D. Vaithiyanathan, R. Seshasayanan, et al. · The Scientific World JOURNAL · 19
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Low power single precision BCD floating–point Vedic multiplier
2019 · V. Ramya, R. Seshasayanan · Microprocessors and Microsystems · 16
Face recognition system based on feature extration
2013 · S. Anith, D. Vaithiyanathan, et al. · International Conference on Information Communication and Embedded Systems · 16
High performance fir filter based on vedic mathematics
2023 · N. Mohana Priya, C. Bennila Thangammal, et al. · International Journal of Systems Assurance Engineering and Management · 15
Denoising Brain Images with the Aid of Discrete Wavelet Transform and Monarch Butterfly Optimization with Different Noises
2018 · T. E. Aravindan, R. Seshasayanan · Journal of Medical Systems · 15
Design and implementation of high throughput, low-complexity MIMO-OFDM transciever
2015 · Ramesh S, R. Seshasayanan · International Conference on Control, Instrumentation, Communication and Computational Technologies · 15
Performance of joint transmit scheme assisted multiple-input multiple-output multi-carrier IDMA system
2013 · K.S. Vishvaksenan, R. Seshasayanan, et al. · Computers & Electrical Engineering · 15
Object tracking system based on invariant features
2013 · S. Mahendran, D. Vaithiyanathan, et al. · International Conference on Communications and Signal Processing (ICCSP) · 14
Design of high speed low power viterbi decoder for TCM system
2013 · J. Nargis, D. Vaithiyanathan, et al. · International Conference on Information Communication and Embedded Systems · 13
WITHDRAWN: Medical image denoising by using discrete wavelet transform: Neutrosophic theory new direction
2018 · T.E. Aravindan, R. Seshasayanan, et al. · Cognitive Systems Research · 11
Optimized architecture for Floating Point computation Unit
2013 · T. Harish Anand, D. Vaithiyanathan, et al. · International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT) · 11
FPGA implemented testbed in 8-by-8 and 2-by-2 OFDM–MIMO channel estimation and design of baseband transceiver
2016 · S. Ramesh, R. Seshasayanan · SpringerPlus · 10
Design, Development and Validation of Smart Sensor Drifting Node with INSAT Telemetry for Oceanographic Applications
2014 · Shijo Zacharia, R. Seshasayanan, et al. · 10
Low power DCT architecture for image compression
2013 · D. Vaithiyanathan, R. Seshasayanan · International Conference on Advanced Computing and Communication Systems (ICACCS) · 10
Notice of Violation of IEEE Publication Principles - A DCT approximation with low complexity for image compression
2013 · K. Saraswathy, D. Vaithiyanathan, et al. · International Conference on Communications and Signal Processing (ICCSP) · 10
Medical image DENOISING scheme using discrete wavelet transform and optimization with different noises
2019 · T.E. Aravindan, R. Seshasayanan · Concurrency and Computation Practice and Experience · 7
High speed low power DWT structure with log based FPU in FPGAs
2013 · D. Vaithiyanathan, R. Seshasayanan · International Conference on Green Computing, Communication and Conservation of Energy · 7
Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding
2017 · R. Nirmaladevi, R. Seshasayanan · Cluster Computing · 4
FPGA implementation of low latency routing algorithm for 3D Network on Chip
2011 · A. Vino Vilmet Rose, R. Seshasayanan, et al. · International Conference on Recent Trends in Information Technology · 4
Observed Variability of Surface Layer in the Central Bay of Bengal:Results of Measurements Using Glider
2017 · Shijo Zacharia, R. Seshasayanan, et al. · Current Science · 3
Works count: 59
Citation count: 364
H-index: 13
I10-index: 20
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