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Heiner Giefers

Observed names: Giefers, Heiner, H. Giefers
ORCID: 0000-0002-5811-6386
Observed ORCID: 0000-0002-5811-6386
OpenAlex ID: A5036729583
Mixed-precision in-memory computing
2018 · Manuel Le Gallo, Abu Sebastian, et al. · Nature Electronics · 485
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Compressed Sensing With Approximate Message Passing Using In-Memory Computing
2018 · Manuel Le Gallo, Abu Sebastian, et al. · IEEE Transactions on Electron Devices · 99
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Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA
2016 · Heiner Giefers, Peter Staar, et al. · IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) · 31
Compressed sensing recovery using computational memory
2017 · M. Le Gallo, A. Sebastian, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28
Accelerating arithmetic kernels with coherent attached FPGA coprocessors
2015 · Heiner Giefers, Raphael Polig, et al. · Design, Automation, and Test in Europe · 19
Accelerating finite difference time domain simulations with reconfigurable dataflow computers
2013 · Heiner Giefers, Christian Plessl, et al. · ACM SIGARCH Computer Architecture News · 16
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
2014 · Heiner Giefers, Raphael Polig, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 15
An FPGA-Based Reconfigurable Mesh Many-Core
2013 · Heiner Giefers, Marco Platzner · IEEE Transactions on Computers · 13
A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware
2015 · C.M. Angerer, R. Polig, et al. · Sustainable Computing Informatics and Systems · 12
Compiling text analytics queries to FPGAs
2014 · Raphael Polig, Kubilay Atasu, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 12
A Many-Core Implementation Based on the Reconfigurable Mesh Model
2007 · Heiner Giefers, Marco Platzner · International Conference on Field Programmable Logic and Applications (FPL) · 12
Accelerating Arithmetic Kernels with Coherent Attached FPGA Coprocessors
2015 · Heiner Giefers, Raphael Polig, et al. · Design, Automation, and Test in Europe · 11
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
2010 · Heiner Giefers, Marco Platzner · International Conference on Field Programmable Logic and Applications (FPL) · 10
ecTALK: Energy efficient coherent transprecision accelerators — The bidirectional long short-term memory neural network case
2018 · Dionysios Diamantopoulos, Heiner Giefers, et al. · IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) · 9
ARMLang: A language and compiler for programming reconfigurable mesh many-cores
2009 · Heiner Giefers, Marco Platzner · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · 9
Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance
2016 · Peter W. J. Staar, Panagiotis Kl. Barkoutsos, et al. · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · 8
A hardware compilation framework for text analytics queries
2017 · Raphael Polig, Kubilay Atasu, et al. · Journal of Parallel and Distributed Computing · 7
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA
2016 · Heiner Giefers, Peter Staar, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 6
FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers
2024 · Christoph Berganski, Felix Jentzsch, et al. · International Conference on Field-Programmable Technology (FPT) · 4
A soft-core processor array for relational operators
2015 · Raphael Polig, Heiner Giefers, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 4
Realizing reconfigurable mesh algorithms on softcore arrays
2008 · Heiner Giefers, Marco Platzner · International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation · 4
NanoStreams: Codesigned microservers for edge analytics in real time
2016 · Giorgis Georgakoudis, Charles Gillan, et al. · International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation · 3
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Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT
2015 · Heiner Giefers, Raphael Polig, et al. · Journal of Signal Processing Systems · 3
Extending the POWER Architecture with Transprecision Co-Processors
2018 · Heiner Giefers, Dionysios Diamantopoulos · IEEE International Symposium on Circuits and Systems proceedings · 2
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.
2010 · Heiner Giefers, Marco Platzner · 1
Works count: 32
Citation count: 826
H-index: 11
I10-index: 13
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