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Author

Arghavan Asad

Observed names: A. Asad, Asad Arghavan, Asad, Arghavan
Institution: Algoma University
ORCID: 0009-0009-0244-8865
Observed ORCIDs: 0009-0009-0244-8865, 0000-0001-9254-9479
OpenAlex ID: A5041995126
A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks
2024 · Rupinder Kaur, Arghavan Asad, et al. · Computers · 39
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A Survey on Neuromorphic Architectures for Running Artificial Intelligence Algorithms
2024 · Seham Al Abdul Wahid, Arghavan Asad, et al. · Electronics · 34
A Survey of Artificial Intelligence Applications in Nuclear Power Plants
2024 · Chaima Jendoubi, Arghavan Asad · IoT · 25
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A Survey on Memory Subsystems for Deep Neural Network Accelerators
2022 · Arghavan Asad, Rupinder Kaur, et al. · Future Internet · 24
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Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy
2017 · Arghavan Asad, Ozcan Ozturk, et al. · Microprocessors and Microsystems · 24
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A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction
2009 · Amir Ehsani Zonouz, Mehrdad Seyrafi, et al. · Euromicro Conference on Digital System Design (DSD) · 23
LLM-Based Threat Detection and Prevention Framework for IoT Ecosystems
2025 · Otoum, Yazan, Asad, Arghavan, et al. · arXiv (Cornell University) · 18
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A Survey of Advancements in Scheduling Techniques for Efficient Deep Learning Computations on GPUs
2025 · Rupinder Kaur, Arghavan Asad, et al. · Electronics · 18
LLMs meet Federated Learning for Scalable and Secure IoT Management
2026 · Yazan Otoum, Arghavan Asad, et al. · International Conference on Communications · 14
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Low-power heterogeneous uncore architecture for future 3D chip-multiprocessors
2018 · Aniseh Dorostkar, Arghavan Asad, et al. · ETRI Journal · 9
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An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors
2017 · Pooneh Safayenikoo, Arghavan Asad, et al. · International Symposium on Quality Electronic Design (ISQED) · 9
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age
2015 · Sobhan Niknam, Arghavan Asad, et al. · International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) · 9
Blockchain Meets Adaptive Honeypots: A Trust-Aware Approach to Next-Gen IoT Security
2025 · Yazan Otoum, Arghavan Asad, et al. · IEEE Transactions on Network Science and Engineering · 8
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A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age
2018 · Arghavan Asad, Aniseh Dorostkar, et al. · EURASIP Journal on Embedded Systems · 8
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Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs
2017 · Pooneh Safayenikoo, Arghavan Asad, et al. · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 8
Efficient Power Consumption using Hybrid Emerging Memory Technology for 3D CMPs
2020 · A. Asad, F. AL-Obaidy, et al. · IEEE Latin American Symposium on Circuits and Systems (LASCAS) · 7
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors
2017 · Fatemeh Arezoomand, Arghavan Asad, et al. · International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) · 7
A Predominant Routing for on-chip networks
2009 · Arghavan Asad, Mehrdad Seyrafi, et al. · International Design and Test Workshop (IDT) · 7
Godiva: green on-chip interconnection for DNNs
2022 · Arghavan Asad, Farah Mohammadi · The Journal of Supercomputing · 6
Improving power-performance via hybrid cache for chip many cores based on neural network prediction technique
2020 · Furat Al-Obaidy, Arghavan Asad, et al. · Microsystem Technologies · 6
Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method
2019 · Furat AL-Obaidy, Arghavan Asad, et al. · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 6
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors
2015 · Arghavan Asad, Ozcan Ozturk, et al. · Euromicro Conference on Digital System Design (DSD) · 6
Quantum Computing Circuit Design: A Tutorial
2024 · Seham Al Abdul Wahid, Arghavan Asad, et al. · International Conference on Advanced Scientific Computing (ICASC) · 5
Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors
2019 · Furat Al-Obaidy, Arghavan Asad, et al. · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 5
Design considerations to affect on shielding effectiveness for conductive enclosure
2011 · Asghar Keshtkar, Amir Maghoul, et al. · IEICE Electronics Express · 5
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Works count: 65
Citation count: 388
H-index: 9
I10-index: 9
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