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Masaya Miyahara

Observed names: M Miyahara, M. MIYAHARA, M. Miyahara, Masaya MIYAHARA, Miyahara, Masaya, 宮原 正也, 宮原, 正也, 宮原正也
Observed institutions: Tokyo Institute of Technology, High Energy Accelerator Research Organization, Japan Advanced Institute of Science and Technology, Japan Broadcasting Corporation (Japan), International Center for Quantum-field Measurement Systems for Studies of the Universe and Particles, Institute of Particle and Nuclear Studies, Canon Medical Systems Corporation (Japan), Nagaoka University of Technology
ORCID: 0000-0002-5748-5921
Observed ORCID: 0000-0002-5748-5921
OpenAlex ID: A5043657126
A low-noise self-calibrating dynamic comparator for high-speed ADCs
2008 · Masaya Miyahara, Yusuke Asada, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 423
Objective picture quality scale (PQS) for image coding
1998 · M. Miyahara, K. Kotani, et al. · IEEE Transactions on Communications · 331
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64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay
2017 · Rui Wu, Ryo Minami, et al. · IEEE Journal of Solid-State Circuits · 142
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry
2012 · Kenichi Okada, Keitarou Kondou, et al. · IEEE Journal of Solid-State Circuits · 137
A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC
2015 · Zhijie Chen, Masaya Miyahara, et al. · Symposium on VLSI Circuits · 128
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding
2014 · Kenichi Okada, Ryo Minami, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 112
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
2013 · Ahmed Musa, Wei Deng, et al. · IEEE Journal of Solid-State Circuits · 109
A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry
2012 · Kenichi Okada, Keitarou Kondou, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 100
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance
2019 · Jian Pang, Shotaro Maki, et al. · IEEE Journal of Solid-State Circuits · 99
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A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique
2011 · James Lin, Masaya Miyahara, et al. · IEEE International Symposium on Circuits and Systems proceedings · 91
A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture
2016 · Teerachot Siriburanon, Satoshi Kondo, et al. · IEEE Journal of Solid-State Circuits · 79
A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain
2016 · Zhijie Chen, Masaya Miyahara, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 75
22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers
2014 · Masaya Miyahara, Ibuki Mano, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 75
A low-offset latched comparator using zero-static power dynamic offset cancellation technique
2009 · Masaya Miyahara, Akira Matsuzawa · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 70
A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC
2016 · Zhijie CHEN, Masaya MIYAHARA, et al. · IEICE Transactions on Electronics · 62
An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier
2017 · Masaya Miyahara, Akira Matsuzawa · Custom Integrated Circuits Conference · 55
Quality assessments for visual service
1988 · M. Miyahara · IEEE Communications Magazine · 49
Block Distortion in Orthogonal Transform Coding--Analysis, Minimization, and Distortion Measure
1985 · M. Miyahara, K. Kotani · IRE Transactions on Communications Systems · 48
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance
2017 · Jian Pang, Shotaro Maki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 46
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay
2016 · Rui Wu, Seitaro Kawai, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 42
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC
2016 · Zule Xu, Masaya Miyahara, et al. · IEEE Journal of Solid-State Circuits · 41
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers
2015 · James Lin, Daehwa Paik, et al. · IEEE Journal of Solid-State Circuits · 36
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers
2016 · Lilan Yu, Masaya Miyahara, et al. · IEEE Journal of Solid-State Circuits · 31
A 0.022mm2 970µW dual-loop injection-locked PLL with −243dB FOM using synthesizable all-digital PVT calibration circuits
2013 · Wei Deng, A. Musa, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 30
A 32-kHz-Reference 2.4-GHz Fractional- N Oversampling PLL With 200-kHz Loop Bandwidth
2021 · Junjun Qiu, Zheng Sun, et al. · IEEE Journal of Solid-State Circuits · 29
Works count: 255
Citation count: 3,055
H-index: 26
I10-index: 49
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