Get started
Author

Alejandro Suanes

Observed name: Suanes, Alejandro
ORCID: 0000-0002-6793-1147
Observed ORCID: 0000-0002-6793-1147
OpenAlex ID: A5046257528
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
2022 · Guillem Cabo, Gerard Candón, et al. · Conference on Design of Circuits and Integrated Systems · 10
PDF
Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology
2023 · Max Doblas, Gerard Candón, et al. · Conference on Design of Circuits and Integrated Systems · 5
PDF
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs
2022 · Alejandro Suanes, Michele Dei, et al. · Integration · 5
PDF
A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation
2021 · Alejandro Suanes, Lluis Teres, et al. · IEEE International Symposium on Circuits and Systems proceedings · 5
A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs
2020 · Alejandro Suanes, Michele Dei, et al. · Conference on Design of Circuits and Integrated Systems · 1
Works count: 6
Citation count: 26
H-index: 4
I10-index: 1
Year
Topic
Type