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René Cumplido

Observed names: Cumplido, Rene, Cumplido, René, R. CUMPLIDO, R. Cumplido, Rene Cumplido
ORCID: 0000-0002-9852-8422
Observed ORCID: 0000-0002-9852-8422
OpenAlex ID: A5046277367
An FPGA Parallel Sorting Architecture for the Burrows Wheeler Transform
2006 · J. Martinez, R. Cumplido, et al. · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 51
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
2013 · Rommel García, Ignacio Algredo-Badillo, et al. · Computers & Electrical Engineering · 50
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
2012 · I. Algredo-Badillo, C. Feregrino-Uribe, et al. · Microprocessors and Microsystems · 50
Pipelined CORDIC Design on FPGA for a Digital Sine and Cosine Waves Generator
2006 · Esteban Garcia, Rene Cumplido, et al. · National Conference on Electrical and Electronics Engineering (ELECO) · 38
Decision Tree Based FPGA-Architecture for Texture Sea State Classification
2006 · Santos Lopez-Estrada, Rene Cumplido · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 32
A versatile linear insertion sorter based on an FIFO scheme
2009 · Roberto Perez-Andrade, Rene Cumplido, et al. · Microelectronics Journal · 28
A lightweight data representation for phishing URLs detection in IoT environments
2022 · Lázaro Bustio-Martínez, Miguel A. Álvarez-Carmona, et al. · Information Sciences · 27
On the design of an FPGA-Based OFDM modulator for IEEE 802.11a
2005 · J. Garcia, R. Cumplido · National Conference on Electrical and Electronics Engineering (ELECO) · 27
An Adaptive Pixel Value Ordering Based Reversible Data Hiding Scheme for Images
2022 · G. Melendez-Melendez, Alicia Morales-Reyes, et al. · Expert Systems with Applications · 26
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard
2010 · Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, et al. · Computers & Electrical Engineering · 23
A secure DWT-based dual watermarking scheme for image authentication and copyright protection
2023 · A. Hernández-Joaquín, G. Melendez-Melendez, et al. · Multimedia Tools and Applications · 22
On the Design of an FPGA-Based OFDM Modulator for IEEE 802.16-2004
2006 · J. Garcia, R. Cumplido · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 22
Compact FPGA hardware architecture for public key encryption in embedded devices
2018 · Luis Rodríguez-Flores, Miguel Morales-Sandoval, et al. · PLoS ONE · 21
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A Versatile Linear Insertion Sorter Based on a FIFO Scheme
2008 · Roberto Perez-Andrade, Rene Cumplido, et al. · IEEE Computer Society Annual Symposium on VLSI · 20
A Compact FPGA‐Based Accelerator for Curve‐Based Cryptography in Wireless Sensor Networks
2021 · Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, et al. · Journal of Sensors · 19
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High payload data-hiding in audio signals based on a modified OFDM approach
2012 · Jose Juan Garcia-Hernandez, Ramon Parra-Michel, et al. · Expert Systems with Applications · 19
Area/performance trade-off analysis of an FPGA digit-serial Montgomery multiplier based on LFSR
2012 · M. Morales-Sandoval, C. Feregrino-Uribe, et al. · Computers & Electrical Engineering · 19
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks
2008 · Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, et al. · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 19
FPGA Hardware Architecture of the Steganographic ConText Technique
2008 · Edgar Gomez-Hernandez, Claudia Feregrino-Uribe, et al. · International Conference on Electronics, Communications, and Computers · 19
On the implementation of an efficient FPGA-based CFAR processor for target detection
2005 · R. Cumplido, C. Torres, et al. · National Conference on Electrical and Electronics Engineering (ELECO) · 19
FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review
2021 · Lázaro Bustio-Martínez, René Cumplido, et al. · ACM Computing Surveys · 18
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture
2006 · Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, et al. · Lecture notes in computer science · 18
A reconfigurable GF(2M) elliptic curve cryptographic coprocessor
2011 · M. Morales-Sandoval, C. Feregrino-Uribe, et al. · Southern Conference on Programmable Logic (SPL) · 17
An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography
2008 · Miguel Morales-Sandoval, Claudia Feregrino-Uribe, et al. · Computers & Electrical Engineering · 17
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+
2024 · Jonathan Lopez-Valdivieso, Rene Cumplido · ACM Transactions on Reconfigurable Technology and Systems · 16
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Works count: 140
Citation count: 1,054
H-index: 19
I10-index: 39
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