Get started
Author

Zaher S. Andraus

Observed names: Andraus, Zaher S., Z.S. Andraus, Zaher Andraus
Observed institution: University of Michigan
OpenAlex ID: A5046558152
AMUSE
2004 · Yoonna Oh, Maher N. Mneimneh, et al. · ACM/IEEE Design Automation Conference (DAC) · 107
Automatic abstraction and verification of verilog models
2004 · Zaher S. Andraus, Karem A. Sakallah · ACM/IEEE Design Automation Conference (DAC) · 65
A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas
2005 · Maher Mneimneh, Inês Lynce, et al. · Lecture notes in computer science · 50
A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas
2008 · Mark Liffiton, Maher Mneimneh, et al. · Constraints · 35
Reveal: A Formal Verification Tool for Verilog Designs
2008 · Zaher S. Andraus, Mark H. Liffiton, et al. · Lecture notes in computer science · 33
Refinement strategies for verification methods based on datapath abstraction
2006 · Zaher S. Andraus, Mark H. Liffiton, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 32
Refinement strategies for verification methods based on datapath abstraction
2006 · Z.S. Andraus, M.H. Liffiton, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 4
Automatic formal verification of control logic in hardware designs
2009 · Karem A. Sakallah, Zaher S. Andraus · 3
Automatic Formal Verification of Control Logic in Hardware Designs
2009 · Andraus, Zaher S. · Deep Blue (University of Michigan)
Works count: 16
Citation count: 329
H-index: 6
I10-index: 6
Year
Topic
Type