Author

Koichi Ishimi

Observed name: K. Ishimi

Institution: Renesas Electronics (Japan)

Observed institutions: Mitsubishi Electric (Japan), Renesas Electronics (Japan)

OpenAlex ID: A5048817163

A multimedia 32 b RISC microprocessor with 16 Mb DRAM

2002 · T. Shimizu, J. Korematu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 57

A 600-MHz Single-Chip Multiprocessor With 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal Memory

2004 · S. Kaneko, H. Kondo, et al. · IEEE Journal of Solid-State Circuits · 35

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

2008 · Hiroyuki Kondo, Mamoru Sakugawa, et al. · IEEE Journal of Solid-State Circuits · 25

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

2009 · Hiroyuki Kondo, Sugako Otani, et al. · IEEE Journal of Solid-State Circuits · 13

Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

2007 · Masami Nakajima, Hiroyuki Kondo, et al. · Symposium on VLSI Circuits · 7

Heterogeneous multicore SoC for secure multimedia applications

2008 · Hiroyuki Kondo, Masami Nakajima, et al. · Custom Integrated Circuits Conference · 1

A 32-bit superscalar microprocessor G/sub MICRO//400 for embedded systems

2002 · J. Korematsu, T. Ueda, et al. · TRON Symposium (TRONSHOW) · 1

Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors

2007 · Masami Nakajima, Koichi Ishimi, et al. · Technical report of IEICE. SDM

Works count: 8

Citation count: 139

H-index: 5

I10-index: 4