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Peter Biolsi

Observed names: P. Biolsi, P.E. Biolsi, Peter E. Biolsi
OpenAlex ID: A5067076216
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
2019 · N. Loubet, S. Kal, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 112
Self-aligned quadruple patterning integration using spacer on spacer pitch splitting at the resist level for sub-32nm pitch applications
2016 · Angélique Raley, Sophie Thibaut, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 24
Challenges and mitigation strategies for resist trim etch in resist-mandrel based SAQP integration scheme
2015 · Nihar Mohanty, Elliott Franke, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 19
Outlook for high-NA EUV patterning: a holistic patterning approach to address upcoming challenges
2022 · Angélique Raley, Lior Huli, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 18
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
2021 · Curtis Durfee, Subhadeep Kal, et al. · ECS Transactions · 17
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Scaling of atomic layer etching of SiO2 in fluorocarbon plasmas: Transient etching and surface roughness
2021 · Xifeng Wang, Mingmei Wang, et al. · Journal of Vacuum Science & Technology A Vacuum Surfaces and Films · 17
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Atomistic simulation analysis of plasma surface activation in wafer-to-wafer oxide fusion bonding
2023 · Hojin Kim, Yu-Hao Tsai, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 15
EPE improvement thru self-alignment via multi-color material integration
2017 · Nihar Mohanty, Jeffrey T. Smith, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 10
Peculiarities of selective isotropic Si etch to SiGe for nanowire and GAA transistors
2019 · Christopher Catano, Nicholas Joy, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 9
Integration of copper with low-k dielectrics for 0.13 μm technology
2003 · J. Gambino, A. Stamper, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 9
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
2021 · Y. Kim, S.-C. Seo, et al. · IEEE Electron Device Letters · 8
Line edge roughness (LER) reduction strategies for EUV self-aligned double patterning (SADP)
2021 · Eric Liu, Katie Lutker-Lee, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 8
Line roughness improvements on EUV 36nm pitch pattern by plasma treatment method
2019 · Toshiharu Wada, Chia-Yun Hsieh, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 8
Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning
2018 · Angélique Raley, Joe Lee, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 7
Self-aligned blocking integration demonstration for critical sub-40nm pitch Mx level patterning
2017 · Angélique Raley, Nihar Mohanty, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 7
A spacer-on-spacer scheme for self-aligned multiple patterning and integration
2016 · Angélique Raley, Sophie Thibaut, et al. · SPIE Newsroom · 7
A sub-50 ps single poly planar bipolar technology
2003 · T.C. Chen, D.D. Tang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
2023 · Curtis Durfee, Ivo Otto IV, et al. · ECS Transactions · 5
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Line edge roughness reduction for EUV self-aligned double patterning by surface modification on spin-on-carbon and tone inversion technique
2021 · Eric Liu, Katie Lutker-Lee, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 5
Roughness and uniformity improvements on self-aligned quadruple patterning technique for 10nm node and beyond by wafer stress engineering
2017 · Eric Liu, Akiteru Ko, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
Overcoming etch challenges related to EUV based patterning (Conference Presentation)
2017 · Andrew W. Metz, Hongyun Cottle, et al. · 5
Defect reduction methodology for advanced copper dual damascene oxide etch
2002 · P. Biolsi, S. Ellinger, et al. · ASMC proceedings · 5
Advanced multiple patterning technologies for high density hexagonal hole arrays
2021 · Nayoung Bae, Sophie Thibaut, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 4
Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning
2018 · Angelique Raley, Joe Lee, et al. · Advanced Etch Technology and Process Integration for Nanopatterning · 4
Investigation into the effect of a PECVD-deposited SiOx chamber coating on the selective, radical-based NF3 etching of TaN with respect to BEOL low-k
2023 · I. V. Otto, C. Vallée, et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 3
Works count: 52
Citation count: 371
H-index: 9
I10-index: 8
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