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Hiromi Hiraishi

Observed names: H. Hiraishi, HIRAISHI, Hiromi, Hiraishi, Hiromi, 平石, 裕実, 裕実 平石
OpenAlex ID: A5078043326
Verification of the Futurebus+ cache coherence protocol
1995 · Edmund M. Clarke, Orna Grumberg, et al. · Formal Methods in System Design · 172
Verification of the Futurebus+ Cache Coherence Protocol**This research was sponsored in part by the Avionics Laboratory, Wright Research and Development Center, Aeronautical Systems Division (AFSC), U.S. Air Force, Wright-Patterson AFB, Ohio 45433-6543 under Contract F33615-90-C-1465, ARPA Order No. 7597 and in part by the National Science Foundation under Grant no. CCR-9005992 and in part by the Semiconductor Research Corporation under Contract 92-DJ-294 and in part by the U.S.-Israeli Binational Science Foundation and in part by a Japan-U.S. cooperative research grant from the Japanese Society for the Promotion of Scientific Research and in part by U.S.-Japan cooperative research grant number INT-90-16694 from the National Science Foundation.The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government.
1993 · Edmund M. Clarke, Orna Grumberg, et al. · Elsevier eBooks · 103
Branching time regular temporal logic for model checking with linear time complexity
2005 · Kiyoharu Hamaguchi, Hiromi Hiraishi, et al. · Springer eBooks · 12
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Vectorized symbolic model checking of computation tree logic for sequential machine verification
1992 · Hiromi Hiraishi, Kiyoharu Hamaguchi, et al. · Lecture notes in computer science · 7
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Branching time regular temporal logic for model checking with linear time complexity
1991 · K. Hamaguchi, H. Hiraishi, et al. · DIMACS series in discrete mathematics and theoretical computer science · 5
Data Compression of the Kanji Character Patterns Digitized on the Hexagonal Mesh
1981 · Shuzo Yajima, Jan L. Goodsell, et al. · IEEE Transactions on Pattern Analysis and Machine Intelligence · 5
Formal verification of speed-dependent asynchronous circuits using symbolic model checking of Branching Time Regular Temporal Logic
1992 · Kiyoharu Hamaguchi, Hiromi Hiraishi, et al. · Lecture notes in computer science · 4
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Locally exhaustive testing of combinational circuits using linear logic circuits
1988 · Hiromi Hiraishi, Kazuhiro Kawahara, et al. · Journal of information processing · 4
Design verification of sequential machines based on a model checking algorithm of e-free regular temporal logic
2018 · Hiraishi, Hiromi · Figshare · 3
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Verification of deadlock free property of high level robot control
2002 · H. Hiraishi · Proceedings - Asian Test Symposium/Proceedings · 3
Design verification of a microprocessor using branching time regular temporal logic
1993 · Kiyoharu Hamaguchi, Hiromi Hiraishi, et al. · Lecture notes in computer science · 3
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Regular temporal logic expressively equivalent to finite automata and its application to logic design verification
1992 · Hiromi Hiraishi, Kiyoharu Hamaguchi, et al. · Journal of information processing · 3
Vectorized model checking for computation tree logic
2005 · Hiromi Hiraishi, Shintaro Meki, et al. · Springer eBooks · 2
Time-space modal model checking towards verification of bit-slice architecture
2002 · H. Hiraishi · Proceedings - Asian Test Symposium/Proceedings · 2
∞-Regular temporal logic and its model checking problem
1992 · Kiyoharu Hamaguchi, Hiromi Hiraishi, et al. · Theoretical Computer Science · 2
Yet more image computations for SMV, the symbolic model verifier
2000 · Hiromi Hiraishi · Systems and Computers in Japan · 1
A Raster-scan Computer Graphic Display Device Having Random-scan Functions with Color Specifying Light Pen Facility
1982 · Hiromi Hiraishi, Shuzo Yajima · Journal of information processing · 1
Gpgpuによる組み合わせ論理回路の入力パタン並列論理シミュレーション
2013 · MORI, Hiroki, HIRAISHI, Hiromi · Institutional Repositories DataBase (IRDB)
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通信状態の可視化によるメッセージ通信型並列プログラムのデバッグ支援ツール
2004 · 渡邉, 淳平, 平石, 裕実 · Institutional Repositories DataBase (IRDB)
クラスタシステムにおける並列バイトニックソートの性能評価
2003 · 屋敷, 康寛, 平石, 裕実 · Institutional Repositories DataBase (IRDB)
Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic
2003 · K. Kawakubo, H. Hiraishi · Proceedings - Asian Test Symposium/Proceedings
Formal verification of self-testing properties of combinational circuits
2002 · K. Kawakubo, K. Tanaka, et al. · Proceedings - Asian Test Symposium/Proceedings
Special Issue on Test and Verification of VLSI
2002 · Hiromi Hiraishi · IEICE Transactions on Information and Systems
Symbolic Model Checking of Deadlock Free Property of Task Control Architecture
2002 · Hiromi Hiraishi · IEICE Transactions on Information and Systems
平成13年度活動概要
2002 · Hiraishi, Hiromi · Institutional Repositories DataBase (IRDB)
Works count: 43
Citation count: 332
H-index: 5
I10-index: 3
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