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Alex V. Veidenbaum

Observed names: A. V. Veidenbaum, A. Veidenbaum, A.V. Veidenbaum, Alex Nicolau, Alex Veidenbaum, Alexander Veidenbaum, Veidenbaum, Alex
Observed institutions: Dartmouth College, University of Illinois Urbana-Champaign, University of California, Irvine, University of Illinois System, University of California System, University of Illinois Chicago, Irvine University
ORCID: 0009-0004-0506-0050
Observed ORCID: 0009-0004-0506-0050
OpenAlex ID: A5079080588
Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors
2009 · Jayram Moorkanikara Nageswaran, Nikil Dutt, et al. · International Joint Conference on Neural Networks (IJCNN) · 90
Profile-based dynamic voltage scheduling using program checkpoints
2003 · A. Azevedo, I. Issenin, et al. · Design, Automation, and Test in Europe · 65
Compiler-directed cache management in multiprocessors
1990 · H. Cheong, A.V. Veidenbaum · Computer · 63
A cache coherence scheme with fast selective invalidation
2003 · H. Cheong, A.V. Veidenbaum · Proceedings - International Symposium on Computer Architecture/Proceedings · 48
The cedar system and an initial performance study
1993 · D. Kuck, W. Jalby, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 47
GraphHD: Efficient graph classification using hyperdimensional computing
2022 · Igor Nunes, Mike Heddes, et al. · Design, Automation, and Test in Europe · 43
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Temperature aware thread migration in 3D architecture with stacked DRAM
2013 · Dali Zhao, H. Homayoun, et al. · International Symposium on Quality Electronic Design (ISQED) · 34
A version control approach to Cache coherence
1989 · Hoichi Cheong, Alex Veidenbaum · International Conference on Supercomputing · 32
Stride-directed prefetching for secondary caches
2002 · S. Kim, A.V. Veidenbaum · Proceedings of the International Conference on Parallel Processing · 30
Power-aware load balancing of large scale MPI applications
2009 · Maja Etinski, Julita Corbalan, et al. · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · 27
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A content aware integer register file organization
2004 · R. Gonzalez, A. Cristal, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 27
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Reducing data cache energy consumption via cached load/store queue
2003 · Dan Nicolaescu, Alex Veidenbaum, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 26
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy
2006 · Dan Nicolaescu, Babak Salamat, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 25
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The Cedar System And An Initial Performance Study
2005 · D. Kuck, E. Davidson, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 23
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
2003 · D. Nicolaescu, Alex Veidenbaum, et al. · 22
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency
2008 · Houman Homayoun, Sudeep Pasricha, et al. · ACM/IEEE Design Automation Conference (DAC) · 19
Guest editors' introduction: application-specific microprocessors
2003 · A. Orailoglu, A. Veidenbaum · IEEE Design & Test of Computers · 19
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management
2010 · Houman Homayoun, Avesta Sasan, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 17
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
2008 · Houman Homayoun, Mohammad Makhzan, et al. · International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) · 17
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits
2008 · Houman Homayoun, Mohammad Makhzan, et al. · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 17
Chief: a parallel simulation environment for parallel systems
2002 · J.D. Bruner, Hoichi Cheong, et al. · International Parallel Processing Symposium · 17
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor
2010 · Houman Homayoun, Aseem Gupta, et al. · Lecture notes in computer science · 15
Energy aware register file implementation through instruction predecode
2004 · J.L. Ayala, M. Lopez-Vallejo, et al. · IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) · 15
Hyperdimensional computing: a framework for stochastic computation and symbolic AI
2024 · Mike Heddes, Igor Nunes, et al. · Journal Of Big Data · 14
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Improving branch prediction accuracy in embedded processors in the presence of context switches
2004 · S. Pasricha, A. Veidenbaum · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · 14
Works count: 93
Citation count: 1,036
H-index: 17
I10-index: 36
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