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Jong-Chan Ha

Observed name: JONG-CHAN HA
Institution: Soongsil University
OpenAlex ID: A5079267409
Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs
2010 · Jae-Young Park, Dae-Woo Kim, et al. · IEEE Transactions on Microwave Theory and Techniques · 4
A Seamless-controlled Digital Pll Using Dual Loops for High Speed Socs
2011 · YOUNG SAN SHIN, JAE-KYUNG WEE, et al. · Journal of Circuits Systems and Computers · 2
A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
2010 · Jae‐Young Park, Dae-Woo Kim, et al. · SIAM International Conference on Data Mining
A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process
2010 · Park Jae-Young, Kim Dae-Woo, et al. · IEICE Technical Report; IEICE Tech. Rep.
Analysis of Chip Performance by Core and I/O SSN Noise on DLL board
2006 · Sung-Gon Cho, Jong-Chan Ha, et al. · Journal of the Microelectronics and Packaging Society
A PLL-Based Clock Generator Using ADC for Targeting SoC/SoP Applications
2005 · Jong-Chan Ha, Taejin Hwang, et al. · International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems
2005 · Jong-Chan Ha, Taejin Hwang, et al. · Journal of the Institute of Electronics Engineers of Korea
Works count: 7
Citation count: 6
H-index: 2
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