Get started
Author

石原 亨

Observed name: Tohru Ishihara
Institution: Kyoto University
OpenAlex ID: A5079645115
An Analysis on a Tradeoff between Reliability and Performance and a Reliable Cache Architecture for Computer Systems
2006 · Sugihara Makoto, 杉原 真, et al. · 電子情報通信学会技術研究報告. SIP, 信号処理 · 2
Real-Time Task Scheduling for Variable Voltage Processor
1998 · 大隈 孝憲, Takanori Okuma, et al. · 電子情報通信学会論文誌. C, エレクトロニクス · 2
Basic Theorems for Variable Voltage Low Power Processors
1998 · Tohru Ishihara, 石原 亨, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路 · 1
Some Experimental Results on Low Power Design with Gated Clock
1995 · 石原 亨, Tohru Ishihara, et al. · 電子情報通信学会技術研究報告. VLD, VLSI設計技術 · 1
Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption
2011 · 高田 純司, Takata Junshi, et al. · 電子情報通信学会技術研究報告. SIP, 信号処理
A Dynamic Management Technique of a Non-uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors
2009 · 石飛 百合子, Tohru Ishihara, et al. · IEICE technical report. Computer systems
An OS-Analyzable Power Consumption Model and Its Generation Technique for Wireless Communication Devices
2009 · Tohru Ishihara, 石原 亨, et al. · IEICE technical report. Dependable computing
Single-Cycle-Accessible Two-Level Cache Architecture
2009 · Yamaguchi Seiichiro, 山口 誠一朗, et al. · 情報処理学会研究報告. SLDM, [システムLSI設計技術]
An Adaptive Multi-Performance Processor and its Evaluation
2008 · Yamaguchi Seiichiro, 山口 誠一朗, et al.
A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
2007 · Yamaguchi Seiichiro, 山口 誠一朗, et al. · 情報処理学会研究報告. SLDM, [システムLSI設計技術]
An On-Chip Bus Architecture for Post-Fabrication Timing Calibration
2007 · 山口 聖貴, Masaki Yamaguchi, et al. · 電子情報通信学会技術研究報告. VLD, VLSI設計技術
A Memory Management Technique for Energy Reduction in Multi-Task Embedded Applications
2007 · 山口 誠一朗, Yamaguchi Seiichiro, et al. · IEICE technical report. Dependable computing
A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits
2007 · 坂本 良太, Ryota Sakamoto, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路
An Energy Characterization Technique for Fast and Accurate Software Power Estimation
2006 · 李 東勲, Donghoon Lee, et al. · IEICE technical report. Computer systems
A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches
2005 · Tohru Ishihara, 石原 亨, et al. · 電子情報通信学会技術研究報告. SIP, 信号処理
A Reliability Evaluation Technique for Soft-Error Susceptible Computer Systems
2005 · 杉原 真, Sugihara Makoto, et al. · 電子情報通信学会技術研究報告. SIP, 信号処理
A Power Optimization Technique for Application Specific Memory Designs
1999 · Tohru Ishihara, 石原 亨, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路
System-Level Energy Optimization for Embedded Systems with a Variable Datapath Width Processor
1998 · 井上 昭彦, Akihiko Inoue, et al. · 電子情報通信学会技術研究報告. VLD, VLSI設計技術
Power Optimization with Variable Voltage Processor
1997 · 石原 亨, Tohru Ishihara, et al. · IEICE technical report. Computer systems
Works count: 19
Citation count: 6
H-index: 2
I10-index:
Year
Topic
Type